Commit d59645d6 authored by Magnus Damm's avatar Magnus Damm Committed by Paul Mundt
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sh: intc - remove redundant irq code for sh03, snapgear and titan



This patch removes redundant board specific interrupt code for boards
using sh775x processors and 4 IRQ lines in "Individual Interrupt Mode"
aka IRLM.

Three boards are affected: sh03, snapgear and titan.

The right way to do this is to use cpu specific code provided by intc.
A nice side effect is that sh03 now compiles, board not BROKEN any more.

Signed-off-by: default avatarMagnus Damm <damm@igel.co.jp>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent ad89f87a
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+1 −1
Original line number Diff line number Diff line
@@ -308,7 +308,7 @@ config SH_MPC1211

config SH_SH03
	bool "Interface CTP/PCI-SH03"
	depends on CPU_SUBTYPE_SH7751 && BROKEN
	depends on CPU_SUBTYPE_SH7751
	select CPU_HAS_IPR_IRQ
	select SYS_SUPPORTS_PCI
	help
+1 −25
Original line number Diff line number Diff line
@@ -15,33 +15,9 @@
#include <asm/sh03/sh03.h>
#include <asm/addrspace.h>

static struct ipr_data ipr_irq_table[] = {
	{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
	{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
	{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
	{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
};

static unsigned long ipr_offsets[] = {
	INTC_IPRD,
};

static struct ipr_desc ipr_irq_desc = {
	.ipr_offsets	= ipr_offsets,
	.nr_offsets	= ARRAY_SIZE(ipr_offsets),

	.ipr_data	= ipr_irq_table,
	.nr_irqs	= ARRAY_SIZE(ipr_irq_table),

	.chip = {
		.name	= "IPR-sh03",
	},
};

static void __init init_sh03_IRQ(void)
{
	ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
	register_ipr_controller(&ipr_irq_desc);
	plat_irq_setup_pins(IRQ_MODE_IRQ);
}

extern void *cf_io_base;
+2 −28
Original line number Diff line number Diff line
@@ -68,37 +68,11 @@ module_init(eraseconfig_init);
 * IRL3 = crypto
 */

static struct ipr_data ipr_irq_table[] = {
	{ IRL0_IRQ, 0, IRL0_IPR_POS, IRL0_PRIORITY },
	{ IRL1_IRQ, 0, IRL1_IPR_POS, IRL1_PRIORITY },
	{ IRL2_IRQ, 0, IRL2_IPR_POS, IRL2_PRIORITY },
	{ IRL3_IRQ, 0, IRL3_IPR_POS, IRL3_PRIORITY },
};

static unsigned long ipr_offsets[] = {
	INTC_IPRD,
};

static struct ipr_desc ipr_irq_desc = {
	.ipr_offsets	= ipr_offsets,
	.nr_offsets	= ARRAY_SIZE(ipr_offsets),

	.ipr_data	= ipr_irq_table,
	.nr_irqs	= ARRAY_SIZE(ipr_irq_table),

	.chip = {
		.name	= "IPR-snapgear",
	},
};

static void __init init_snapgear_IRQ(void)
{
	/* enable individual interrupt mode for externals */
	ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);

	printk("Setup SnapGear IRQ/IPR ...\n");

	register_ipr_controller(&ipr_irq_desc);
	/* enable individual interrupt mode for externals */
	plat_irq_setup_pins(IRQ_MODE_IRQ);
}

/*
+1 −29
Original line number Diff line number Diff line
@@ -12,38 +12,10 @@
#include <asm/titan.h>
#include <asm/io.h>

static struct ipr_data ipr_irq_table[] = {
	/* IRQ, IPR idx, shift, prio */
	{ TITAN_IRQ_WAN,   3, 12, 8 },	/* eth0 (WAN) */
	{ TITAN_IRQ_LAN,   3,  8, 8 },	/* eth1 (LAN) */
	{ TITAN_IRQ_MPCIA, 3,  4, 8 },	/* mPCI A (top) */
	{ TITAN_IRQ_USB,   3,  0, 8 },	/* mPCI B (bottom), USB */
};

static unsigned long ipr_offsets[] = { /* stolen from setup-sh7750.c */
	0xffd00004UL,	/* 0: IPRA */
	0xffd00008UL,	/* 1: IPRB */
	0xffd0000cUL,	/* 2: IPRC */
	0xffd00010UL,	/* 3: IPRD */
};

static struct ipr_desc ipr_irq_desc = {
	.ipr_offsets	= ipr_offsets,
	.nr_offsets	= ARRAY_SIZE(ipr_offsets),

	.ipr_data	= ipr_irq_table,
	.nr_irqs	= ARRAY_SIZE(ipr_irq_table),

	.chip = {
		.name	= "IPR-titan",
	},
};
static void __init init_titan_irq(void)
{
	/* enable individual interrupt mode for externals */
	ipr_irq_enable_irlm();
	/* register ipr irqs */
	register_ipr_controller(&ipr_irq_desc);
	plat_irq_setup_pins(IRQ_MODE_IRQ);
}

static struct sh_machine_vector mv_titan __initmv = {
+10 −4
Original line number Diff line number Diff line
@@ -282,13 +282,19 @@ void __init plat_irq_setup(void)
#define INTC_ICR	0xffd00000UL
#define INTC_ICR_IRLM   (1<<7)

/* enable individual interrupt mode for external interupts */
void __init ipr_irq_enable_irlm(void)
void __init plat_irq_setup_pins(int mode)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
	BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
	return;
#endif
	register_intc_controller(&intc_desc_irlm);

	switch (mode) {
	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
		ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
		register_intc_controller(&intc_desc_irlm);
		break;
	default:
		BUG();
	}
}
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