Commit d5aaa0bc authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-fixes-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy fixes from Vinod Koul:

 - Qualcomm QMP driver fixes for null deref on suspend, bogus supplies
   fix and reset entries fix

 - BCM usb driver init array fix

 - cadence array offset fix

 - starfive link configuration fix

 - config dependency fix for rockchip driver

 - freescale reset signal fix before pll lock

 - tegra driver fix for error pointer check

* tag 'phy-fixes-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: tegra: xusb: Add error pointer check in xusb.c
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Fix X1E80100 resets entries
  phy: freescale: imx8m-pcie: Do CMN_RST just before PHY PLL lock check
  phy: phy-rockchip-samsung-hdptx: Depend on CONFIG_COMMON_CLK
  phy: ti: phy-j721e-wiz: fix usxgmii configuration
  phy: starfive: jh7110-usb: Fix link configuration to controller
  phy: qcom: qmp-pcie: drop bogus x1e80100 qref supplies
  phy: qcom: qmp-combo: move driver data initialisation earlier
  phy: qcom: qmp-usbc: fix NULL-deref on runtime suspend
  phy: qcom: qmp-usb-legacy: fix NULL-deref on runtime suspend
  phy: qcom: qmp-usb: fix NULL-deref on runtime suspend
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: add missing x1e80100 pipediv2 clocks
  phy: usb: disable COMMONONN for dual mode
  phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register
  phy: usb: Fix missing elements in BCM4908 USB init array
parents e8529dcb e70d2677

Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml

+3 −2
Original line number Diff line number Diff line
@@ -154,8 +154,6 @@ allOf: 
              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen3x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen3x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

    then:

      properties:

        clocks:
@@ -171,6 +169,8 @@ allOf: 
              - qcom,sc8280xp-qmp-gen3x1-pcie-phy

              - qcom,sc8280xp-qmp-gen3x2-pcie-phy

              - qcom,sc8280xp-qmp-gen3x4-pcie-phy

              - qcom,x1e80100-qmp-gen3x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x4-pcie-phy

    then:

      properties:
@@ -201,6 +201,7 @@ allOf: 
              - qcom,sm8550-qmp-gen4x2-pcie-phy

              - qcom,sm8650-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x2-pcie-phy

              - qcom,x1e80100-qmp-gen4x4-pcie-phy

    then:

      properties:

        resets:

drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c

+9 −3
Original line number Diff line number Diff line
@@ -153,7 +153,9 @@ static void xhci_soft_reset(struct brcm_usb_init_params *params, 
	} else {

		USB_CTRL_SET(ctrl, USB_PM, XHC_SOFT_RESETB);

		/* Required for COMMONONN to be set */

		USB_XHCI_GBL_UNSET(xhci_gbl, GUSB2PHYCFG, U2_FREECLK_EXISTS);

		if (params->supported_port_modes != USB_CTLR_MODE_DRD)

			USB_XHCI_GBL_UNSET(xhci_gbl, GUSB2PHYCFG,

					   U2_FREECLK_EXISTS);

	}

}
@@ -328,7 +330,11 @@ static void usb_init_common_7216(struct brcm_usb_init_params *params) 
	/* 1 millisecond - for USB clocks to settle down */

	usleep_range(1000, 2000);



	/* Disable PHY when port is suspended */

	/*

	 * Disable PHY when port is suspended

	 * Does not work in DRD mode

	 */

	if (params->supported_port_modes != USB_CTLR_MODE_DRD)

		USB_CTRL_SET(ctrl, P0_U2PHY_CFG1, COMMONONN);



	usb_wake_enable_7216(params, false);

drivers/phy/broadcom/phy-brcm-usb-init.c

+2 −0
Original line number Diff line number Diff line
@@ -220,6 +220,8 @@ usb_reg_bits_map_table[BRCM_FAMILY_COUNT][USB_CTRL_SELECTOR_COUNT] = { 
		0, /* USB_CTRL_SETUP_SCB2_EN_MASK */

		0, /* USB_CTRL_SETUP_SS_EHCI64BIT_EN_MASK */

		0, /* USB_CTRL_SETUP_STRAP_IPP_SEL_MASK */

		0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT0_MASK */

		0, /* USB_CTRL_SETUP_OC3_DISABLE_PORT1_MASK */

		0, /* USB_CTRL_SETUP_OC3_DISABLE_MASK */

		0, /* USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK */

		0, /* USB_CTRL_USB_PM_BDC_SOFT_RESETB_MASK */

drivers/phy/cadence/phy-cadence-sierra.c

+11 −10
Original line number Diff line number Diff line
@@ -174,8 +174,9 @@ 
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150

#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151

#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152

#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x158

#define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG		0x158

#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG		0x159

#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x15C

#define SIERRA_DEQ_PICTRL_PREG				0x161

#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170

#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171
@@ -1733,7 +1734,7 @@ static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1797,7 +1798,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1874,7 +1875,7 @@ static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -1941,7 +1942,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2012,7 +2013,7 @@ static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2079,7 +2080,7 @@ static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2140,7 +2141,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2215,7 +2216,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},
@@ -2284,7 +2285,7 @@ static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = { 
	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},

	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},

	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},

	{0x5E82, SIERRA_DEQ_OPENEYE_CTRL_PREG},

	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},

	{0x002B, SIERRA_CPI_TRIM_PREG},

	{0x0003, SIERRA_EPI_CTRL_PREG},

	{0x803F, SIERRA_SDFILT_H2L_A_PREG},

drivers/phy/freescale/phy-fsl-imx8m-pcie.c

+5 −5
Original line number Diff line number Diff line
@@ -141,11 +141,6 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
			   IMX8MM_GPR_PCIE_REF_CLK_PLL);

	usleep_range(100, 200);



	/* Do the PHY common block reset */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_CMN_RST,

			   IMX8MM_GPR_PCIE_CMN_RST);



	switch (imx8_phy->drvdata->variant) {

	case IMX8MP:

		reset_control_deassert(imx8_phy->perst);
@@ -156,6 +151,11 @@ static int imx8_pcie_phy_power_on(struct phy *phy) 
		break;

	}



	/* Do the PHY common block reset */

	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,

			   IMX8MM_GPR_PCIE_CMN_RST,

			   IMX8MM_GPR_PCIE_CMN_RST);



	/* Polling to check the phy is ready or not. */

	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,

				 val, val == ANA_PLL_DONE, 10, 20000);