Commit d5ab32e9 authored by Vikas Gupta's avatar Vikas Gupta Committed by Jakub Kicinski
Browse files

bnxt_en: Add delay to handle Downstream Port Containment (DPC) AER 



In case of DPC, after issuing the hot reset, the
kernel waits for 100ms for the device to complete
the reset. However on some older chips, the firmware
may take up to 1 second to complete the reset, only
after which the driver can restart the card.

Introduce delay of 900ms to handle this scenario on
the older chipsets.

Signed-off-by: default avatarVikas Gupta <vikas.gupta@broadcom.com>
Reviewed-by: default avatarMichael Chan <michael.chan@broadcom.com>
Reviewed-by: default avatarSomnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: default avatarPavan Chebbi <pavan.chebbi@broadcom.com>
Acked-by: default avatarPaolo Abeni <pabeni@redhat.com>
Link: https://lore.kernel.org/r/20240402093753.331120-2-pavan.chebbi@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 04172043

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+4 −0
Original line number Diff line number Diff line
@@ -15550,6 +15550,10 @@ static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev) 


	netdev_info(bp->dev, "PCI Slot Reset\n");



	if (!(bp->flags & BNXT_FLAG_CHIP_P5_PLUS) &&

	    test_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state))

		msleep(900);



	rtnl_lock();



	if (pci_enable_device(pdev)) {