Commit d5c1b4b4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2025-11-15' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Weekly fixes, amdgpu and vmwgfx making up the most of it, along with
  panthor and i915/xe.

  Seems about right for this time of development, nothing major
  outstanding.

  client:
   - Fix description of module parameter

  panthor:
   - Flush writes before mapping buffers

  vmwgfx:
   - Improve command validation
   - Improve ref counting
   - Fix cursor-plane support

  amdgpu:
   - Disallow P2P DMA for GC 12 DCC surfaces
   - ctx error handling fix
   - UserQ fixes
   - VRR fix
   - ISP fix
   - JPEG 5.0.1 fix

  amdkfd:
   - Save area check fix
   - Fix GPU mappings for APU after prefetch

  i915:
   - Fix PSR's pipe to vblank conversion
   - Disable Panel Replay on MST links

  xe:
   - New HW workarounds affecting PTL and WCL platforms

* tag 'drm-fixes-2025-11-15' of https://gitlab.freedesktop.org/drm/kernel:
  drm/client: fix MODULE_PARM_DESC string for "active"
  drm/i915/dp_mst: Disable Panel Replay
  drm/amdkfd: Fix GPU mappings for APU after prefetch
  drm/amdkfd: relax checks for over allocation of save area
  drm/amdgpu/jpeg: Add parse_cs for JPEG5_0_1
  drm/amd/amdgpu: Ensure isp_kernel_buffer_alloc() creates a new BO
  drm/amd/display: Allow VRR params change if unsynced with the stream
  drm/amdgpu: fix lock warning in amdgpu_userq_fence_driver_process
  drm/amdgpu: jump to the correct label on failure
  drm/amdgpu: disable peer-to-peer access for DCC-enabled GC12 VRAM surfaces
  drm/xe/xe3lpg: Extend Wa_15016589081 for xe3lpg
  drm/xe/xe3: Extend wa_14023061436
  drm/xe/xe3: Add WA_14024681466 for Xe3_LPG
  drm/i915/psr: fix pipe to vblank conversion
  drm/panthor: Flush shmem writes before mapping buffers CPU-uncached
  drm/vmwgfx: Restore Guest-Backed only cursor plane support
  drm/vmwgfx: Use kref in vmw_bo_dirty
  drm/vmwgfx: Validate command header size against SVGA_CMD_MAX_DATASIZE
parents ccc00118 362a7d4f

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+1 −1
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 
		r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv,

						&num_scheds, &scheds);

		if (r)

			goto cleanup_entity;

			goto error_free_entity;

	}



	/* disable load balance if the hw engine retains context among dependent jobs */

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

+12 −0
Original line number Diff line number Diff line
@@ -82,6 +82,18 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, 
	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);



	/*

	 * Disable peer-to-peer access for DCC-enabled VRAM surfaces on GFX12+.

	 * Such buffers cannot be safely accessed over P2P due to device-local

	 * compression metadata. Fallback to system-memory path instead.

	 * Device supports GFX12 (GC 12.x or newer)

	 * BO was created with the AMDGPU_GEM_CREATE_GFX12_DCC flag

	 *

	 */

	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0) &&

	    bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC)

		attach->peer2peer = false;



	if (!amdgpu_dmabuf_is_xgmi_accessible(attach_adev, bo) &&

	    pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)

		attach->peer2peer = false;

drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c

+2 −0
Original line number Diff line number Diff line
@@ -280,6 +280,8 @@ int isp_kernel_buffer_alloc(struct device *dev, u64 size, 
	if (ret)

		return ret;



	/* Ensure *bo is NULL so a new BO will be created */

	*bo = NULL;

	ret = amdgpu_bo_create_kernel(adev,

				      size,

				      ISP_MC_ADDR_ALIGN,

drivers/gpu/drm/amd/amdgpu/amdgpu_userq_fence.c

+3 −2
Original line number Diff line number Diff line
@@ -151,15 +151,16 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d 
{

	struct amdgpu_userq_fence *userq_fence, *tmp;

	struct dma_fence *fence;

	unsigned long flags;

	u64 rptr;

	int i;



	if (!fence_drv)

		return;



	spin_lock_irqsave(&fence_drv->fence_list_lock, flags);

	rptr = amdgpu_userq_fence_read(fence_drv);



	spin_lock(&fence_drv->fence_list_lock);

	list_for_each_entry_safe(userq_fence, tmp, &fence_drv->fences, link) {

		fence = &userq_fence->base;
@@ -174,7 +175,7 @@ void amdgpu_userq_fence_driver_process(struct amdgpu_userq_fence_driver *fence_d 
		list_del(&userq_fence->link);

		dma_fence_put(fence);

	}

	spin_unlock(&fence_drv->fence_list_lock);

	spin_unlock_irqrestore(&fence_drv->fence_list_lock, flags);

}



void amdgpu_userq_fence_driver_destroy(struct kref *ref)

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

+1 −0
Original line number Diff line number Diff line
@@ -878,6 +878,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_1_dec_ring_vm_funcs = { 
	.get_rptr = jpeg_v5_0_1_dec_ring_get_rptr,

	.get_wptr = jpeg_v5_0_1_dec_ring_get_wptr,

	.set_wptr = jpeg_v5_0_1_dec_ring_set_wptr,

	.parse_cs = amdgpu_jpeg_dec_parse_cs,

	.emit_frame_size =

		SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +

		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +