Commit d5ceb949 authored by Kevin Xie's avatar Kevin Xie Committed by Bjorn Helgaas
Browse files

PCI: Add PCIE_RESET_CONFIG_DEVICE_WAIT_MS waiting time value 

Add the PCIE_RESET_CONFIG_DEVICE_WAIT_MS macro to define the minimum
waiting time between exit from a conventional reset and sending the
first configuration request to the device.

As described in PCIe r6.0, sec 6.6.1 <Conventional Reset>, there are two
different use cases of the value:

   - "With a Downstream Port that does not support Link speeds greater
     than 5.0 GT/s, software must wait a minimum of 100 ms following exit
     from a Conventional Reset before sending a Configuration Request to
     the device immediately below that Port."

   - "With a Downstream Port that supports Link speeds greater than
     5.0 GT/s, software must wait a minimum of 100 ms after Link training
     completes before sending a Configuration Request to the device
     immediately below that Port."

[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20240328091835.14797-21-minda.chen@starfivetech.com


Signed-off-by: default avatarKevin Xie <kevin.xie@starfivetech.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarMason Huo <mason.huo@starfivetech.com>
parent d76ef053

drivers/pci/pci.h

+15 −0
Original line number Diff line number Diff line
@@ -22,6 +22,21 @@ 
 */

#define PCIE_PME_TO_L2_TIMEOUT_US	10000



/*

 * PCIe r6.0, sec 6.6.1 <Conventional Reset>

 *

 * - "With a Downstream Port that does not support Link speeds greater

 *    than 5.0 GT/s, software must wait a minimum of 100 ms following exit

 *    from a Conventional Reset before sending a Configuration Request to

 *    the device immediately below that Port."

 *

 * - "With a Downstream Port that supports Link speeds greater than

 *    5.0 GT/s, software must wait a minimum of 100 ms after Link training

 *    completes before sending a Configuration Request to the device

 *    immediately below that Port."

 */

#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS	100



extern const unsigned char pcie_link_speed[];

extern bool pci_early_dump;