Commit d5dd8c52 authored by Lukasz Majewski's avatar Lukasz Majewski Committed by Abel Vesa
Browse files

clk: vf610: Add support for the Ethernet switch clocks 



The vf610 device has built in the MoreThanIP L2 switch. For proper
operation it is required to enable ESW and MAC table lookup
clocks.

The MAC table spans from 0x400E_C000 for 0x4000 and it is necessary
to provide clocks for each AIPS1-"slot", which size is 0x1000
(hence four separate entries).

Those can be enabled via clock gating CCM_CCGR10 register
(0x4006_B068).

Signed-off-by: default avatarLukasz Majewski <lukma@nabladev.com>
Reviewed-by: default avatarPeng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260129095442.1646748-5-lukma@nabladev.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@oss.qualcomm.com>
parent 77f18a1f

drivers/clk/imx/clk-vf610.c

+6 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@ 
 * include/dt-bindings/clock/vf610-clock.h

 * It shall be the value of the last defined clock +1

 */

#define VF610_CLK_END 191

#define VF610_CLK_END 196



#define CCM_CCR			(ccm_base + 0x00)

#define CCM_CSR			(ccm_base + 0x04)
@@ -320,6 +320,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 
	clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);

	clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));

	clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));

	clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));

	clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));

	clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));

	clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));

	clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));



	clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));