Commit d5fe2fec authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Borislav Petkov (AMD)
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EDAC: Add a driver for the AMD Versal NET DDR controller 



Add a driver for the AMD Versal NET DDR memory controller which supports
single bit error correction, double bit error detection and other system
errors from various IP subsystems (e.g., RPU, NOCs, HNICX, PL).

The driver listens for notifications from the NMC (Network management
controller) using RPMsg (Remote Processor Messaging).

The channel used for communicating to RPMsg is named "error_edac".  Upon
receipt of a notification, the driver sends a RAS event trace.

  [ bp:
    - Fixup title
    - Rewrite commit message
    - Fixup Kconfig text
    - Zap unused defines and align them
    - Simplify rpmsg_cb() considerably
    - Drop silly double-brackets in conditionals
    - Use proper void * type in mcdi_request()
    - Do not clear chinfo in rpmsg_probe() unnecessarily
    - Fix indentation
    - Do a proper err unwind path in init_versalnet()
    - Redo the error unwind path in mc_probe() properly
    - Fix the ordering in mc_remove()
    ]

Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/20250908115649.22903-1-shubhrajyoti.datta@amd.com
Link: https://lore.kernel.org/r/20250703173105.GLaGa-WQCESDNsqygm@fat_crate.local
parent 8d978222

MAINTAINERS

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@@ -27631,6 +27631,13 @@ S: Maintained 
F:	Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml

F:	drivers/edac/versal_edac.c









XILINX VERSALNET EDAC DRIVER









M:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>









S:	Maintained









F:	Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml









F:	drivers/edac/versalnet_edac.c









F:	include/linux/cdx/edac_cdx_pcol.h

















XILINX WATCHDOG DRIVER









M:	Srinivas Neeli <srinivas.neeli@amd.com>









R:	Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>

























drivers/edac/Kconfig



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@@ -584,4 +584,12 @@ config EDAC_CORTEX_A72







	  The detected and reported errors are from reading CPU/L2 memory error









	  syndrome registers.



















config EDAC_VERSALNET









	tristate "AMD VersalNET DDR Controller"









	depends on CDX_CONTROLLER && ARCH_ZYNQMP









	help









	  Support for single bit error correction, double bit error detection









	  and other system errors from various IP subsystems like RPU, NOCs,









	  HNICX, PL on the AMD Versal NET DDR memory controller.



















endif # EDAC
























drivers/edac/Makefile



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@@ -88,4 +88,5 @@ obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o







obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o









obj-$(CONFIG_EDAC_VERSAL)		+= versal_edac.o









obj-$(CONFIG_EDAC_LOONGSON)		+= loongson_edac.o









obj-$(CONFIG_EDAC_VERSALNET)		+= versalnet_edac.o









obj-$(CONFIG_EDAC_CORTEX_A72)		+= a72_edac.o
























drivers/edac/versalnet_edac.c
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include/linux/cdx/edac_cdx_pcol.h
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/* SPDX-License-Identifier: GPL-2.0









 *









 * Driver for AMD network controllers and boards









 *









 * Copyright (C) 2021, Xilinx, Inc.









 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.









 */



















#ifndef MC_CDX_PCOL_H









#define MC_CDX_PCOL_H









#include  <linux/cdx/mcdi.h>



















#define MC_CMD_EDAC_GET_DDR_CONFIG_OUT_WORD_LENGTH_LEN		4









/* Number of registers for the DDR controller */









#define MC_CMD_GET_DDR_CONFIG_OFST	4









#define MC_CMD_GET_DDR_CONFIG_LEN	4



















/***********************************/









/* MC_CMD_EDAC_GET_DDR_CONFIG









 * Provides detailed configuration for the DDR controller of the given index.









 */









#define MC_CMD_EDAC_GET_DDR_CONFIG 0x3



















/* MC_CMD_EDAC_GET_DDR_CONFIG_IN msgrequest */









#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_OFST		0









#define MC_CMD_EDAC_GET_DDR_CONFIG_IN_CONTROLLER_INDEX_LEN		4



















#endif /* MC_CDX_PCOL_H */