Commit d608703f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:
 "Fixes for some SoC clk drivers:

   - Define the gate clk for the OTG PHY on Rockchip RK3576 so the nvmem
     driver actually works

   - Initialize clk_hw_onecell_data::num before accessing the 'hws'
     array to keep UBSAN happy

   - Fix a perf degradation on the Allwinner D1 MMC clk that was making
     things half bad

   - Fix the Allwinner SNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro to have
     proper order of arguments"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
  clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in probe()
  clk: sunxi-ng: fix order of arguments in clock macro
  clk: rockchip: rk3576: define clk_otp_phy_g
parents 4a95bc12 6a568805

drivers/clk/clk-s2mps11.c

+2 −1
Original line number Diff line number Diff line
@@ -137,6 +137,8 @@ static int s2mps11_clk_probe(struct platform_device *pdev) 
	if (!clk_data)

		return -ENOMEM;



	clk_data->num = S2MPS11_CLKS_NUM;



	switch (hwid) {

	case S2MPS11X:

		s2mps11_reg = S2MPS11_REG_RTC_CTRL;
@@ -186,7 +188,6 @@ static int s2mps11_clk_probe(struct platform_device *pdev) 
		clk_data->hws[i] = &s2mps11_clks[i].hw;

	}



	clk_data->num = S2MPS11_CLKS_NUM;

	of_clk_add_hw_provider(s2mps11_clks->clk_np, of_clk_hw_onecell_get,

			       clk_data);

drivers/clk/rockchip/clk-rk3576.c

+2 −0
Original line number Diff line number Diff line
@@ -541,6 +541,8 @@ static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { 
			RK3576_CLKGATE_CON(5), 14, GFLAGS),

	GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,

			RK3576_CLKGATE_CON(5), 15, GFLAGS),

	GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,

			RK3576_CLKGATE_CON(6), 0, GFLAGS),

	COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0,

			RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS,

			RK3576_CLKGATE_CON(6), 3, GFLAGS),

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

+25 −19
Original line number Diff line number Diff line
@@ -412,18 +412,22 @@ static const struct clk_parent_data mmc0_mmc1_parents[] = { 
	{ .hw = &pll_periph0_2x_clk.common.hw },

	{ .hw = &pll_audio1_div2_clk.common.hw },

};

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc0_mmc1_parents, 0x830,

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",

					       mmc0_mmc1_parents, 0x830,

					       0, 4,		/* M */

					       8, 2,		/* P */

					       24, 3,		/* mux */

					       BIT(31),		/* gate */

					       2,		/* post-div */

					       0);



static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc0_mmc1_parents, 0x834,

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",

					       mmc0_mmc1_parents, 0x834,

					       0, 4,		/* M */

					       8, 2,		/* P */

					       24, 3,		/* mux */

					       BIT(31),		/* gate */

					       2,		/* post-div */

					       0);



static const struct clk_parent_data mmc2_parents[] = {
@@ -433,11 +437,13 @@ static const struct clk_parent_data mmc2_parents[] = { 
	{ .hw = &pll_periph0_800M_clk.common.hw },

	{ .hw = &pll_audio1_div2_clk.common.hw },

};

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc2_parents, 0x838,

static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc2_parents,

					       0x838,

					       0, 4,		/* M */

					       8, 2,		/* P */

					       24, 3,		/* mux */

					       BIT(31),		/* gate */

					       2,		/* post-div */

					       0);



static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", psi_ahb_hws,

drivers/clk/sunxi-ng/ccu_mp.h

+23 −2
Original line number Diff line number Diff line
@@ -52,6 +52,28 @@ struct ccu_mp { 
		}							\

	}



#define SUNXI_CCU_MP_DATA_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, \

						_reg,			\

						_mshift, _mwidth,	\

						_pshift, _pwidth,	\

						_muxshift, _muxwidth,	\

						_gate, _postdiv, _flags)\

	struct ccu_mp _struct = {					\

		.enable	= _gate,					\

		.m	= _SUNXI_CCU_DIV(_mshift, _mwidth),		\

		.p	= _SUNXI_CCU_DIV(_pshift, _pwidth),		\

		.mux	= _SUNXI_CCU_MUX(_muxshift, _muxwidth),		\

		.fixed_post_div	= _postdiv,				\

		.common	= {						\

			.reg		= _reg,				\

			.features	= CCU_FEATURE_FIXED_POSTDIV,	\

			.hw.init	= CLK_HW_INIT_PARENTS_DATA(_name, \

							_parents,	\

							&ccu_mp_ops,	\

							_flags),	\

		}							\

	}



#define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg,	\

				   _mshift, _mwidth,			\

				   _pshift, _pwidth,			\
@@ -109,8 +131,7 @@ struct ccu_mp { 
					     _mshift, _mwidth,		\

					     _pshift, _pwidth,		\

					     _muxshift, _muxwidth,	\

					     _gate, _features,		\

					     _flags)			\

					     _gate, _flags, _features)	\

	struct ccu_mp _struct = {					\

		.enable	= _gate,					\

		.m	= _SUNXI_CCU_DIV(_mshift, _mwidth),		\