Commit d6219e1c authored by Niranjana Vishwanathapura's avatar Niranjana Vishwanathapura Committed by Matt Roper
Browse files

drm/xe: Add Indirect Ring State support 



When Indirect Ring State is enabled, the Ring Buffer state and
Batch Buffer state are context save/restored to/from Indirect
Ring State instead of the LRC. The Indirect Ring State is a 4K
page mapped in global GTT at a 4K aligned address. This address
is programmed in the INDIRECT_RING_STATE register of the
corresponding context's LRC.

v2: Fix kernel-doc, add bspec reference
v3: Fix typo in commit text

Bspec: 67296, 67139
Signed-off-by: default avatarNiranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240507224255.5059-3-niranjana.vishwanathapura@intel.com
parent 85cfc412

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -125,6 +125,7 @@ 
#define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)



#define RING_CONTEXT_CONTROL(base)		XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)

#define	  CTX_CTRL_INDIRECT_RING_STATE_ENABLE	REG_BIT(4)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	REG_BIT(3)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	REG_BIT(0)

drivers/gpu/drm/xe/regs/xe_lrc_layout.h

+7 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#define CTX_RING_TAIL			(0x06 + 1)

#define CTX_RING_START			(0x08 + 1)

#define CTX_RING_CTL			(0x0a + 1)

#define CTX_INDIRECT_RING_STATE		(0x26 + 1)

#define CTX_PDP0_UDW			(0x30 + 1)

#define CTX_PDP0_LDW			(0x32 + 1)
@@ -23,4 +24,10 @@ 
#define CTX_INT_SRC_REPORT_REG		(CTX_LRI_INT_REPORT_PTR + 3)

#define CTX_INT_SRC_REPORT_PTR		(CTX_LRI_INT_REPORT_PTR + 4)



#define INDIRECT_CTX_RING_HEAD		(0x02 + 1)

#define INDIRECT_CTX_RING_TAIL		(0x04 + 1)

#define INDIRECT_CTX_RING_START		(0x06 + 1)

#define INDIRECT_CTX_RING_START_UDW	(0x08 + 1)

#define INDIRECT_CTX_RING_CTL		(0x0a + 1)



#endif

drivers/gpu/drm/xe/xe_gt.c

+3 −3
Original line number Diff line number Diff line
@@ -160,7 +160,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 


	if (q->hwe->class == XE_ENGINE_CLASS_RENDER)

		/* Big enough to emit all of the context's 3DSTATE */

		bb = xe_bb_new(gt, xe_lrc_size(gt_to_xe(gt), q->hwe->class), false);

		bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false);

	else

		/* Just pick a large BB size */

		bb = xe_bb_new(gt, SZ_4K, false);
@@ -244,7 +244,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) 
		xe_tuning_process_lrc(hwe);



		default_lrc = drmm_kzalloc(&xe->drm,

					   xe_lrc_size(xe, hwe->class),

					   xe_gt_lrc_size(gt, hwe->class),

					   GFP_KERNEL);

		if (!default_lrc)

			return -ENOMEM;
@@ -294,7 +294,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) 
		xe_map_memcpy_from(xe, default_lrc,

				   &q->lrc[0].bo->vmap,

				   xe_lrc_pphwsp_offset(&q->lrc[0]),

				   xe_lrc_size(xe, hwe->class));

				   xe_gt_lrc_size(gt, hwe->class));



		gt->default_lrc[hwe->class] = default_lrc;

put_nop_q:

drivers/gpu/drm/xe/xe_gt.h

+7 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


#include <drm/drm_util.h>



#include "xe_device.h"

#include "xe_device_types.h"

#include "xe_hw_engine.h"
@@ -58,6 +59,12 @@ struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 
				     u16 instance,

				     bool logical);



static inline bool xe_gt_has_indirect_ring_state(struct xe_gt *gt)

{

	return gt->info.has_indirect_ring_state &&

	       xe_device_uc_enabled(gt_to_xe(gt));

}



static inline bool xe_gt_is_media_type(struct xe_gt *gt)

{

	return gt->info.type == XE_GT_TYPE_MEDIA;

drivers/gpu/drm/xe/xe_gt_types.h

+4 −2
Original line number Diff line number Diff line
@@ -110,8 +110,6 @@ struct xe_gt { 
	struct {

		/** @info.type: type of GT */

		enum xe_gt_type type;

		/** @info.id: Unique ID of this GT within the PCI Device */

		u8 id;

		/** @info.reference_clock: clock frequency */

		u32 reference_clock;

		/** @info.engine_mask: mask of engines present on GT */
@@ -124,6 +122,10 @@ struct xe_gt { 
		u64 __engine_mask;

		/** @info.gmdid: raw GMD_ID value from hardware */

		u32 gmdid;

		/** @info.id: Unique ID of this GT within the PCI Device */

		u8 id;

		/** @info.has_indirect_ring_state: GT has indirect ring state support */

		u8 has_indirect_ring_state:1;

	} info;



	/**