Commit d64522b5 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules 



Add clock and reset definitions required to support the DSI and LCDC
hardware blocks on the RZ/V2N SoC. This includes new core clocks, clock
dividers, module clocks, and reset entries, as well as PLL and divider
configurations specific to these peripherals.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-2-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 79276fb0

drivers/clk/renesas/r9a09g056-cpg.c

+64 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
 */



#include <linux/clk-provider.h>

#include <linux/clk/renesas.h>

#include <linux/device.h>

#include <linux/init.h>

#include <linux/kernel.h>
@@ -29,6 +30,7 @@ enum clk_ids { 
	CLK_PLLDTY,

	CLK_PLLCA55,

	CLK_PLLETH,

	CLK_PLLDSI,

	CLK_PLLGPU,



	/* Internal Core Clocks */
@@ -47,6 +49,7 @@ enum clk_ids { 
	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,

	CLK_PLLDTY_DIV8,

	CLK_PLLDTY_DIV16,

	CLK_PLLETH_DIV_250_FIX,

	CLK_PLLETH_DIV_125_FIX,

	CLK_CSDIV_PLLETH_GBE0,
@@ -55,6 +58,9 @@ enum clk_ids { 
	CLK_SMUX2_GBE0_RXCLK,

	CLK_SMUX2_GBE1_TXCLK,

	CLK_SMUX2_GBE1_RXCLK,

	CLK_CDIV4_PLLETH_LPCLK,

	CLK_PLLETH_LPCLK_GEAR,

	CLK_PLLDSI_GEAR,

	CLK_PLLGPU_GEAR,



	/* Module Clocks */
@@ -77,6 +83,26 @@ static const struct clk_div_table dtable_2_16[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_2_32[] = {

	{0, 2},

	{1, 4},

	{2, 6},

	{3, 8},

	{4, 10},

	{5, 12},

	{6, 14},

	{7, 16},

	{8, 18},

	{9, 20},

	{10, 22},

	{11, 24},

	{12, 26},

	{13, 28},

	{14, 30},

	{15, 32},

	{0, 0},

};



static const struct clk_div_table dtable_2_64[] = {

	{0, 2},

	{1, 4},
@@ -93,6 +119,17 @@ static const struct clk_div_table dtable_2_100[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_16_128[] = {

	{0, 16},

	{1, 32},

	{2, 64},

	{3, 128},

	{0, 0},

};



RZV2H_CPG_PLL_DSI_LIMITS(rzv2n_cpg_pll_dsi_limits);

#define PLLDSI		PLL_PACK_LIMITS(0xc0, 1, 0, &rzv2n_cpg_pll_dsi_limits)



/* Mux clock tables */

static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };

static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
@@ -113,6 +150,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),

	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),

	DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),

	DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI),

	DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU),



	/* Internal Core Clocks */
@@ -134,6 +172,7 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),

	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),

	DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8),

	DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),



	DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4),

	DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2),
@@ -145,6 +184,12 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
	DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk),

	DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk),

	DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk),

	DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4),

	DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_LPCLK,

		  CSDIV0_DIVCTL2, dtable_16_128),



	DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI,

		       CSDIV1_DIVCTL2, dtable_2_32),



	DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64),
@@ -289,6 +334,22 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,

						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("dsi_0_pclk",			CLK_PLLDTY_DIV16, 14, 8, 7, 8,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_vclk1",			CLK_PLLDSI_GEAR, 14, 10, 7, 10,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_lpclk",			CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("dsi_0_pllref_clk",		CLK_QEXTAL, 14, 12, 7, 12,

						BUS_MSTOP(9, BIT(14) | BIT(15))),

	DEF_MOD("lcdc_0_clk_a",			CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_p",			CLK_PLLDTY_DIV16, 14, 14, 7, 14,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("lcdc_0_clk_d",			CLK_PLLDSI_GEAR, 14, 15, 7, 15,

						BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))),

	DEF_MOD("gpu_0_clk",			CLK_PLLGPU_GEAR, 15, 0, 7, 16,

						BUS_MSTOP(3, BIT(4))),

	DEF_MOD("gpu_0_axi_clk",		CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
@@ -335,6 +396,9 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(13, 7, 6, 8),		/* DSI_0_PRESETN */

	DEF_RST(13, 8, 6, 9),		/* DSI_0_ARESETN */

	DEF_RST(13, 12, 6, 13),		/* LCDC_0_RESET_N */

	DEF_RST(13, 13, 6, 14),		/* GPU_0_RESETN */

	DEF_RST(13, 14, 6, 15),		/* GPU_0_AXI_RESETN */

	DEF_RST(13, 15, 6, 16),		/* GPU_0_ACE_RESETN */