Commit d669ec6b authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
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clk: samsung: clk-pll: simplify samsung_pll_lock_wait() 



readl_relaxed_poll_timeout_atomic() has been updated in 2023 in
commit 7349a69c ("iopoll: Do not use timekeeping in
read_poll_timeout_atomic()") to avoid usage of timekeeping APIs. It
also never used udelay() when no delay was given.

With the implementation avoiding timekeeping APIs, and with a caller
not passing a delay, the timeout argument simply becomes a loop
counter.

Therefore the code here can be simplified to unconditionally use
readl_relaxed_poll_timeout_atomic(). The difference being the last
argument, the timeout (loop counter). Simply adjust it to pass the
more generous counter in all cases.

This change also allows us to drop all code around the
pll_early_timeout variable as it is unused now.

Reviewed-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20251013-samsung-clk-pll-simplification-v2-1-b9aab610878c@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 25e47663

drivers/clk/samsung/clk-pll.c

+10 −31
Original line number Diff line number Diff line
@@ -11,14 +11,12 @@ 
#include <linux/iopoll.h>

#include <linux/delay.h>

#include <linux/slab.h>

#include <linux/timekeeping.h>

#include <linux/clk-provider.h>

#include <linux/io.h>

#include "clk.h"

#include "clk-pll.h"



#define PLL_TIMEOUT_US		20000U

#define PLL_TIMEOUT_LOOPS	1000000U

#define PLL_TIMEOUT_LOOPS	20000U



struct samsung_clk_pll {

	struct clk_hw		hw;
@@ -71,20 +69,11 @@ static int samsung_pll_determine_rate(struct clk_hw *hw, 
	return 0;

}



static bool pll_early_timeout = true;



static int __init samsung_pll_disable_early_timeout(void)

{

	pll_early_timeout = false;

	return 0;

}

arch_initcall(samsung_pll_disable_early_timeout);



/* Wait until the PLL is locked */

static int samsung_pll_lock_wait(struct samsung_clk_pll *pll,

				 unsigned int reg_mask)

{

	int i, ret;

	int ret;

	u32 val;



	/*
@@ -93,25 +82,15 @@ static int samsung_pll_lock_wait(struct samsung_clk_pll *pll, 
	 * initialized, another when the timekeeping is suspended. udelay() also

	 * cannot be used when the clocksource is not running on arm64, since

	 * the current timer is used as cycle counter. So a simple busy loop

	 * is used here in that special cases. The limit of iterations has been

	 * derived from experimental measurements of various PLLs on multiple

	 * Exynos SoC variants. Single register read time was usually in range

	 * 0.4...1.5 us, never less than 0.4 us.

	 * is used here.

	 * The limit of iterations has been derived from experimental

	 * measurements of various PLLs on multiple Exynos SoC variants. Single

	 * register read time was usually in range 0.4...1.5 us, never less than

	 * 0.4 us.

	 */

	if (pll_early_timeout || timekeeping_suspended) {

		i = PLL_TIMEOUT_LOOPS;

		while (i-- > 0) {

			if (readl_relaxed(pll->con_reg) & reg_mask)

				return 0;



			cpu_relax();

		}

		ret = -ETIMEDOUT;

	} else {

	ret = readl_relaxed_poll_timeout_atomic(pll->con_reg, val,

					val & reg_mask, 0, PLL_TIMEOUT_US);

	}



						val & reg_mask, 0,

						PLL_TIMEOUT_LOOPS);

	if (ret < 0)

		pr_err("Could not lock PLL %s\n", clk_hw_get_name(&pll->hw));