Commit d6797831 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu model updates from Borislav Petkov:

 - Flip the logic to add feature names to /proc/cpuinfo to having to
   explicitly specify the flag if there's a valid reason to show it in
   /proc/cpuinfo

 - Switch a bunch of Intel x86 model checking code to the new CPU model
   defines

 - Fixes and cleanups

* tag 'x86_cpu_for_v6.11_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines
  x86/cpufeatures: Flip the /proc/cpuinfo appearance logic
  x86/CPU/AMD: Always inline amd_clear_divider()
  x86/mce/inject: Add missing MODULE_DESCRIPTION() line
  perf/x86/rapl: Switch to new Intel CPU model defines
  x86/boot: Switch to new Intel CPU model defines
  x86/cpu: Switch to new Intel CPU model defines
  perf/x86/intel: Switch to new Intel CPU model defines
  x86/virt/tdx: Switch to new Intel CPU model defines
  x86/PCI: Switch to new Intel CPU model defines
  x86/cpu/intel: Switch to new Intel CPU model defines
  x86/platform/intel-mid: Switch to new Intel CPU model defines
  x86/pconfig: Remove unused MKTME pconfig code
  x86/cpu: Remove useless work in detect_tme_early()
parents 2439a5ea 34b3fc55

arch/x86/boot/cpucheck.c

+1 −1
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ int check_knl_erratum(void) 
	 */

	if (!is_intel() ||

	    cpu.family != 6 ||

	    cpu.model != INTEL_FAM6_XEON_PHI_KNL)

	    cpu.model != 0x57 /*INTEL_XEON_PHI_KNL*/)

		return 0;



	/*

arch/x86/events/intel/core.c

+106 −106
Original line number Diff line number Diff line
@@ -4698,8 +4698,8 @@ static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs); 
static inline bool intel_pmu_broken_perf_cap(void)

{

	/* The Perf Metric (Bit 15) is always cleared */

	if ((boot_cpu_data.x86_model == INTEL_FAM6_METEORLAKE) ||

	    (boot_cpu_data.x86_model == INTEL_FAM6_METEORLAKE_L))

	if (boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||

	    boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)

		return true;



	return false;
@@ -5187,35 +5187,35 @@ static __init void intel_clovertown_quirk(void) 
}



static const struct x86_cpu_desc isolation_ucodes[] = {

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL,		 3, 0x0000001f),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L,		 1, 0x0000001e),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,		 2, 0x00000037),

	INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G,		 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D,		 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X,		 1, 0x0b000014),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 3, 0x00000021),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 4, 0x00000000),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 5, 0x00000000),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 6, 0x00000000),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		 7, 0x00000000),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X,		11, 0x00000000),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,		 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,		 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,		10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,		11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L,		12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,		10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,		11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,		12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE,		13, 0x0000004e),

	INTEL_CPU_DESC(INTEL_HASWELL,		 3, 0x0000001f),

	INTEL_CPU_DESC(INTEL_HASWELL_L,		 1, 0x0000001e),

	INTEL_CPU_DESC(INTEL_HASWELL_G,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 2, 0x00000037),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_BROADWELL_G,	 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_BROADWELL_X,	 1, 0x0b000014),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 3, 0x00000021),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 4, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 5, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 6, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 7, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		11, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_L,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_SKYLAKE,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		13, 0x0000004e),

	{}

};
@@ -5232,9 +5232,9 @@ static __init void intel_pebs_isolation_quirk(void) 
}



static const struct x86_cpu_desc pebs_ucodes[] = {

	INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE,		7, 0x00000028),

	INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,	6, 0x00000618),

	INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X,	7, 0x0000070c),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE,	7, 0x00000028),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	6, 0x00000618),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	7, 0x0000070c),

	{}

};
@@ -6238,19 +6238,19 @@ __init int intel_pmu_init(void) 
	/*

	 * Install the hw-cache-events table:

	 */

	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_CORE_YONAH:

	switch (boot_cpu_data.x86_vfm) {

	case INTEL_CORE_YONAH:

		pr_cont("Core events, ");

		name = "core";

		break;



	case INTEL_FAM6_CORE2_MEROM:

	case INTEL_CORE2_MEROM:

		x86_add_quirk(intel_clovertown_quirk);

		fallthrough;



	case INTEL_FAM6_CORE2_MEROM_L:

	case INTEL_FAM6_CORE2_PENRYN:

	case INTEL_FAM6_CORE2_DUNNINGTON:

	case INTEL_CORE2_MEROM_L:

	case INTEL_CORE2_PENRYN:

	case INTEL_CORE2_DUNNINGTON:

		memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -6262,9 +6262,9 @@ __init int intel_pmu_init(void) 
		name = "core2";

		break;



	case INTEL_FAM6_NEHALEM:

	case INTEL_FAM6_NEHALEM_EP:

	case INTEL_FAM6_NEHALEM_EX:

	case INTEL_NEHALEM:

	case INTEL_NEHALEM_EP:

	case INTEL_NEHALEM_EX:

		memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -6296,11 +6296,11 @@ __init int intel_pmu_init(void) 
		name = "nehalem";

		break;



	case INTEL_FAM6_ATOM_BONNELL:

	case INTEL_FAM6_ATOM_BONNELL_MID:

	case INTEL_FAM6_ATOM_SALTWELL:

	case INTEL_FAM6_ATOM_SALTWELL_MID:

	case INTEL_FAM6_ATOM_SALTWELL_TABLET:

	case INTEL_ATOM_BONNELL:

	case INTEL_ATOM_BONNELL_MID:

	case INTEL_ATOM_SALTWELL:

	case INTEL_ATOM_SALTWELL_MID:

	case INTEL_ATOM_SALTWELL_TABLET:

		memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -6313,11 +6313,11 @@ __init int intel_pmu_init(void) 
		name = "bonnell";

		break;



	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_D:

	case INTEL_FAM6_ATOM_SILVERMONT_MID:

	case INTEL_FAM6_ATOM_AIRMONT:

	case INTEL_FAM6_ATOM_AIRMONT_MID:

	case INTEL_ATOM_SILVERMONT:

	case INTEL_ATOM_SILVERMONT_D:

	case INTEL_ATOM_SILVERMONT_MID:

	case INTEL_ATOM_AIRMONT:

	case INTEL_ATOM_AIRMONT_MID:

		memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,

			sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
@@ -6335,8 +6335,8 @@ __init int intel_pmu_init(void) 
		name = "silvermont";

		break;



	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_GOLDMONT_D:

	case INTEL_ATOM_GOLDMONT:

	case INTEL_ATOM_GOLDMONT_D:

		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
@@ -6362,7 +6362,7 @@ __init int intel_pmu_init(void) 
		name = "goldmont";

		break;



	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:

	case INTEL_ATOM_GOLDMONT_PLUS:

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
@@ -6391,9 +6391,9 @@ __init int intel_pmu_init(void) 
		name = "goldmont_plus";

		break;



	case INTEL_FAM6_ATOM_TREMONT_D:

	case INTEL_FAM6_ATOM_TREMONT:

	case INTEL_FAM6_ATOM_TREMONT_L:

	case INTEL_ATOM_TREMONT_D:

	case INTEL_ATOM_TREMONT:

	case INTEL_ATOM_TREMONT_L:

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -6420,7 +6420,7 @@ __init int intel_pmu_init(void) 
		name = "Tremont";

		break;



	case INTEL_FAM6_ATOM_GRACEMONT:

	case INTEL_ATOM_GRACEMONT:

		intel_pmu_init_grt(NULL);

		intel_pmu_pebs_data_source_grt();

		x86_pmu.pebs_latency_data = adl_latency_data_small;
@@ -6432,8 +6432,8 @@ __init int intel_pmu_init(void) 
		name = "gracemont";

		break;



	case INTEL_FAM6_ATOM_CRESTMONT:

	case INTEL_FAM6_ATOM_CRESTMONT_X:

	case INTEL_ATOM_CRESTMONT:

	case INTEL_ATOM_CRESTMONT_X:

		intel_pmu_init_grt(NULL);

		x86_pmu.extra_regs = intel_cmt_extra_regs;

		intel_pmu_pebs_data_source_cmt();
@@ -6446,9 +6446,9 @@ __init int intel_pmu_init(void) 
		name = "crestmont";

		break;



	case INTEL_FAM6_WESTMERE:

	case INTEL_FAM6_WESTMERE_EP:

	case INTEL_FAM6_WESTMERE_EX:

	case INTEL_WESTMERE:

	case INTEL_WESTMERE_EP:

	case INTEL_WESTMERE_EX:

		memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
@@ -6477,8 +6477,8 @@ __init int intel_pmu_init(void) 
		name = "westmere";

		break;



	case INTEL_FAM6_SANDYBRIDGE:

	case INTEL_FAM6_SANDYBRIDGE_X:

	case INTEL_SANDYBRIDGE:

	case INTEL_SANDYBRIDGE_X:

		x86_add_quirk(intel_sandybridge_quirk);

		x86_add_quirk(intel_ht_bug);

		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
@@ -6491,7 +6491,7 @@ __init int intel_pmu_init(void) 
		x86_pmu.event_constraints = intel_snb_event_constraints;

		x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;

		x86_pmu.pebs_aliases = intel_pebs_aliases_snb;

		if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)

		if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)

			x86_pmu.extra_regs = intel_snbep_extra_regs;

		else

			x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -6517,8 +6517,8 @@ __init int intel_pmu_init(void) 
		name = "sandybridge";

		break;



	case INTEL_FAM6_IVYBRIDGE:

	case INTEL_FAM6_IVYBRIDGE_X:

	case INTEL_IVYBRIDGE:

	case INTEL_IVYBRIDGE_X:

		x86_add_quirk(intel_ht_bug);

		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,

		       sizeof(hw_cache_event_ids));
@@ -6534,7 +6534,7 @@ __init int intel_pmu_init(void) 
		x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;

		x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;

		x86_pmu.pebs_prec_dist = true;

		if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)

		if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)

			x86_pmu.extra_regs = intel_snbep_extra_regs;

		else

			x86_pmu.extra_regs = intel_snb_extra_regs;
@@ -6556,10 +6556,10 @@ __init int intel_pmu_init(void) 
		break;





	case INTEL_FAM6_HASWELL:

	case INTEL_FAM6_HASWELL_X:

	case INTEL_FAM6_HASWELL_L:

	case INTEL_FAM6_HASWELL_G:

	case INTEL_HASWELL:

	case INTEL_HASWELL_X:

	case INTEL_HASWELL_L:

	case INTEL_HASWELL_G:

		x86_add_quirk(intel_ht_bug);

		x86_add_quirk(intel_pebs_isolation_quirk);

		x86_pmu.late_ack = true;
@@ -6589,10 +6589,10 @@ __init int intel_pmu_init(void) 
		name = "haswell";

		break;



	case INTEL_FAM6_BROADWELL:

	case INTEL_FAM6_BROADWELL_D:

	case INTEL_FAM6_BROADWELL_G:

	case INTEL_FAM6_BROADWELL_X:

	case INTEL_BROADWELL:

	case INTEL_BROADWELL_D:

	case INTEL_BROADWELL_G:

	case INTEL_BROADWELL_X:

		x86_add_quirk(intel_pebs_isolation_quirk);

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -6631,8 +6631,8 @@ __init int intel_pmu_init(void) 
		name = "broadwell";

		break;



	case INTEL_FAM6_XEON_PHI_KNL:

	case INTEL_FAM6_XEON_PHI_KNM:

	case INTEL_XEON_PHI_KNL:

	case INTEL_XEON_PHI_KNM:

		memcpy(hw_cache_event_ids,

		       slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs,
@@ -6651,15 +6651,15 @@ __init int intel_pmu_init(void) 
		name = "knights-landing";

		break;



	case INTEL_FAM6_SKYLAKE_X:

	case INTEL_SKYLAKE_X:

		pmem = true;

		fallthrough;

	case INTEL_FAM6_SKYLAKE_L:

	case INTEL_FAM6_SKYLAKE:

	case INTEL_FAM6_KABYLAKE_L:

	case INTEL_FAM6_KABYLAKE:

	case INTEL_FAM6_COMETLAKE_L:

	case INTEL_FAM6_COMETLAKE:

	case INTEL_SKYLAKE_L:

	case INTEL_SKYLAKE:

	case INTEL_KABYLAKE_L:

	case INTEL_KABYLAKE:

	case INTEL_COMETLAKE_L:

	case INTEL_COMETLAKE:

		x86_add_quirk(intel_pebs_isolation_quirk);

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -6708,16 +6708,16 @@ __init int intel_pmu_init(void) 
		name = "skylake";

		break;



	case INTEL_FAM6_ICELAKE_X:

	case INTEL_FAM6_ICELAKE_D:

	case INTEL_ICELAKE_X:

	case INTEL_ICELAKE_D:

		x86_pmu.pebs_ept = 1;

		pmem = true;

		fallthrough;

	case INTEL_FAM6_ICELAKE_L:

	case INTEL_FAM6_ICELAKE:

	case INTEL_FAM6_TIGERLAKE_L:

	case INTEL_FAM6_TIGERLAKE:

	case INTEL_FAM6_ROCKETLAKE:

	case INTEL_ICELAKE_L:

	case INTEL_ICELAKE:

	case INTEL_TIGERLAKE_L:

	case INTEL_TIGERLAKE:

	case INTEL_ROCKETLAKE:

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));

		memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
@@ -6752,13 +6752,13 @@ __init int intel_pmu_init(void) 
		name = "icelake";

		break;



	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

	case INTEL_SAPPHIRERAPIDS_X:

	case INTEL_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_glc_extra_regs;

		fallthrough;

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:

	case INTEL_GRANITERAPIDS_X:

	case INTEL_GRANITERAPIDS_D:

		intel_pmu_init_glc(NULL);

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_rwc_extra_regs;
@@ -6776,11 +6776,11 @@ __init int intel_pmu_init(void) 
		name = "sapphire_rapids";

		break;



	case INTEL_FAM6_ALDERLAKE:

	case INTEL_FAM6_ALDERLAKE_L:

	case INTEL_FAM6_RAPTORLAKE:

	case INTEL_FAM6_RAPTORLAKE_P:

	case INTEL_FAM6_RAPTORLAKE_S:

	case INTEL_ALDERLAKE:

	case INTEL_ALDERLAKE_L:

	case INTEL_RAPTORLAKE:

	case INTEL_RAPTORLAKE_P:

	case INTEL_RAPTORLAKE_S:

		/*

		 * Alder Lake has 2 types of CPU, core and atom.

		 *
@@ -6838,8 +6838,8 @@ __init int intel_pmu_init(void) 
		name = "alderlake_hybrid";

		break;



	case INTEL_FAM6_METEORLAKE:

	case INTEL_FAM6_METEORLAKE_L:

	case INTEL_METEORLAKE:

	case INTEL_METEORLAKE_L:

		intel_pmu_init_hybrid(hybrid_big_small);



		x86_pmu.pebs_latency_data = mtl_latency_data_small;

arch/x86/events/rapl.c

+45 −45
Original line number Diff line number Diff line
@@ -766,50 +766,50 @@ static struct rapl_model model_amd_hygon = { 


static const struct x86_cpu_id rapl_model_match[] __initconst = {

	X86_MATCH_FEATURE(X86_FEATURE_RAPL,	&model_amd_hygon),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE,		&model_snb),

	X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X,	&model_snbep),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE,		&model_snb),

	X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X,		&model_snbep),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL,		&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L,		&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G,		&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL,		&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G,		&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL,	&model_knl),

	X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM,	&model_knl),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT,	&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D,	&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS,	&model_hsw),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,		&model_hsx),

	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&model_spr),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&model_spr),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L,	&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE_H,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(ARROWLAKE,		&model_skl),

	X86_MATCH_INTEL_FAM6_MODEL(LUNARLAKE_M,		&model_skl),

	X86_MATCH_VFM(INTEL_SANDYBRIDGE,	&model_snb),

	X86_MATCH_VFM(INTEL_SANDYBRIDGE_X,	&model_snbep),

	X86_MATCH_VFM(INTEL_IVYBRIDGE,		&model_snb),

	X86_MATCH_VFM(INTEL_IVYBRIDGE_X,	&model_snbep),

	X86_MATCH_VFM(INTEL_HASWELL,		&model_hsw),

	X86_MATCH_VFM(INTEL_HASWELL_X,		&model_hsx),

	X86_MATCH_VFM(INTEL_HASWELL_L,		&model_hsw),

	X86_MATCH_VFM(INTEL_HASWELL_G,		&model_hsw),

	X86_MATCH_VFM(INTEL_BROADWELL,		&model_hsw),

	X86_MATCH_VFM(INTEL_BROADWELL_G,	&model_hsw),

	X86_MATCH_VFM(INTEL_BROADWELL_X,	&model_hsx),

	X86_MATCH_VFM(INTEL_BROADWELL_D,	&model_hsx),

	X86_MATCH_VFM(INTEL_XEON_PHI_KNL,	&model_knl),

	X86_MATCH_VFM(INTEL_XEON_PHI_KNM,	&model_knl),

	X86_MATCH_VFM(INTEL_SKYLAKE_L,		&model_skl),

	X86_MATCH_VFM(INTEL_SKYLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_SKYLAKE_X,		&model_hsx),

	X86_MATCH_VFM(INTEL_KABYLAKE_L,		&model_skl),

	X86_MATCH_VFM(INTEL_KABYLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_CANNONLAKE_L,	&model_skl),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT,	&model_hsw),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D,	&model_hsw),

	X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS,	&model_hsw),

	X86_MATCH_VFM(INTEL_ICELAKE_L,		&model_skl),

	X86_MATCH_VFM(INTEL_ICELAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_ICELAKE_D,		&model_hsx),

	X86_MATCH_VFM(INTEL_ICELAKE_X,		&model_hsx),

	X86_MATCH_VFM(INTEL_COMETLAKE_L,	&model_skl),

	X86_MATCH_VFM(INTEL_COMETLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_TIGERLAKE_L,	&model_skl),

	X86_MATCH_VFM(INTEL_TIGERLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_ALDERLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_ALDERLAKE_L,	&model_skl),

	X86_MATCH_VFM(INTEL_ATOM_GRACEMONT,	&model_skl),

	X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X,	&model_spr),

	X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X,	&model_spr),

	X86_MATCH_VFM(INTEL_RAPTORLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_RAPTORLAKE_P,	&model_skl),

	X86_MATCH_VFM(INTEL_RAPTORLAKE_S,	&model_skl),

	X86_MATCH_VFM(INTEL_METEORLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_METEORLAKE_L,	&model_skl),

	X86_MATCH_VFM(INTEL_ARROWLAKE_H,	&model_skl),

	X86_MATCH_VFM(INTEL_ARROWLAKE,		&model_skl),

	X86_MATCH_VFM(INTEL_LUNARLAKE_M,	&model_skl),

	{},

};

MODULE_DEVICE_TABLE(x86cpu, rapl_model_match);

arch/x86/include/asm/cpu_device_id.h

+4 −4
Original line number Diff line number Diff line
@@ -280,10 +280,10 @@ struct x86_cpu_desc { 
	u32	x86_microcode_rev;

};



#define INTEL_CPU_DESC(model, stepping, revision) {		\

	.x86_family		= 6,				\

	.x86_vendor		= X86_VENDOR_INTEL,		\

	.x86_model		= (model),			\

#define INTEL_CPU_DESC(vfm, stepping, revision) {		\

	.x86_family		= VFM_FAMILY(vfm),		\

	.x86_vendor		= VFM_VENDOR(vfm),		\

	.x86_model		= VFM_MODEL(vfm),		\

	.x86_stepping		= (stepping),			\

	.x86_microcode_rev	= (revision),			\

}

arch/x86/include/asm/cpufeatures.h

+400 −400

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