Commit d6c94157 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2024-06-22' of https://gitlab.freedesktop.org/drm/kernel 

Pull drm fixes from Dave Airlie:
 "Still pretty quiet, two weeks worth of amdgpu fixes, with one i915 and
  one xe. I didn't get the drm-misc-fixes tree PR this week, but there
  was only one fix queued and I think it can wait another week, so seems
  pretty normal.

  xe:
   - Fix for invalid register access

  i915:
   - Fix conditions for joiner usage, it's not possible with eDP MSO

  amdgpu:
   - Fix display idle optimization race
   - Fix GPUVM TLB flush locking scope
   - IPS fix
   - GFX 9.4.3 harvesting fix
   - Runtime pm fix for shared buffers
   - DCN 3.5.x fixes
   - USB4 fix
   - RISC-V clang fix
   - Silence UBSAN warnings
   - MES11 fix
   - PSP 14.0.x fix"

* tag 'drm-fixes-2024-06-22' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/vf: Don't touch GuC irq registers if using memory irqs
  drm/amdgpu: init TA fw for psp v14
  drm/amdgpu: cleanup MES11 command submission
  drm/amdgpu: fix UBSAN warning in kv_dpm.c
  drm/radeon: fix UBSAN warning in kv_dpm.c
  drm/amd/display: Disable CONFIG_DRM_AMD_DC_FP for RISC-V with clang
  drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIA
  drm/amd/display: change dram_clock_latency to 34us for dcn35
  drm/amd/display: Change dram_clock_latency to 34us for dcn351
  drm/amdgpu: revert "take runtime pm reference when we attach a buffer" v2
  drm/amdgpu: Indicate CU havest info to CP
  drm/amd/display: prevent register access while in IPS
  drm/amdgpu: fix locking scope when flushing tlb
  drm/amd/display: Remove redundant idle optimization check
  drm/i915/mso: using joiner is not possible with eDP MSO
parents 264efe48 d1913b86

drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c

+0 −34
Original line number Diff line number Diff line
@@ -41,8 +41,6 @@ 
#include <linux/dma-buf.h>

#include <linux/dma-fence-array.h>

#include <linux/pci-p2pdma.h>

#include <linux/pm_runtime.h>

#include "amdgpu_trace.h"



/**

 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
@@ -58,42 +56,11 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, 
	struct drm_gem_object *obj = dmabuf->priv;

	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);

	int r;



	if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0)

		attach->peer2peer = false;



	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);

	trace_amdgpu_runpm_reference_dumps(1, __func__);

	if (r < 0)

		goto out;



	return 0;



out:

	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

	trace_amdgpu_runpm_reference_dumps(0, __func__);

	return r;

}



/**

 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation

 *

 * @dmabuf: DMA-buf where we remove the attachment from

 * @attach: the attachment to remove

 *

 * Called when an attachment is removed from the DMA-buf.

 */

static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,

				  struct dma_buf_attachment *attach)

{

	struct drm_gem_object *obj = dmabuf->priv;

	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);

	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);



	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

	trace_amdgpu_runpm_reference_dumps(0, __func__);

}



/**
@@ -267,7 +234,6 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, 


const struct dma_buf_ops amdgpu_dmabuf_ops = {

	.attach = amdgpu_dma_buf_attach,

	.detach = amdgpu_dma_buf_detach,

	.pin = amdgpu_dma_buf_pin,

	.unpin = amdgpu_dma_buf_unpin,

	.map_dma_buf = amdgpu_dma_buf_map,

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+0 −2
Original line number Diff line number Diff line
@@ -181,7 +181,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd 
	amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,

			       seq, flags | AMDGPU_FENCE_FLAG_INT);

	pm_runtime_get_noresume(adev_to_drm(adev)->dev);

	trace_amdgpu_runpm_reference_dumps(1, __func__);

	ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];

	if (unlikely(rcu_dereference_protected(*ptr, 1))) {

		struct dma_fence *old;
@@ -309,7 +308,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) 
		dma_fence_put(fence);

		pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);

		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);

		trace_amdgpu_runpm_reference_dumps(0, __func__);

	} while (last_seq != seq);



	return true;

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+34 −32
Original line number Diff line number Diff line
@@ -684,12 +684,17 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 
	struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

	unsigned int ndw;

	signed long r;

	int r;

	uint32_t seq;



	if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready ||

	    !down_read_trylock(&adev->reset_domain->sem)) {

	/*

	 * A GPU reset should flush all TLBs anyway, so no need to do

	 * this while one is ongoing.

	 */

	if (!down_read_trylock(&adev->reset_domain->sem))

		return 0;



	if (!adev->gmc.flush_pasid_uses_kiq || !ring->sched.ready) {

		if (adev->gmc.flush_tlb_needs_extra_type_2)

			adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,

								 2, all_hub,
@@ -703,9 +708,8 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 
		adev->gmc.gmc_funcs->flush_gpu_tlb_pasid(adev, pasid,

							 flush_type, all_hub,

							 inst);

		return 0;

	}



		r = 0;

	} else {

		/* 2 dwords flush + 8 dwords fence */

		ndw = kiq->pmf->invalidate_tlbs_size + 8;
@@ -733,13 +737,11 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 


		amdgpu_ring_commit(ring);

		spin_unlock(&adev->gfx.kiq[inst].ring_lock);

	r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);

	if (r < 1) {

		dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);

		if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {

			dev_err(adev->dev, "timeout waiting for kiq fence\n");

			r = -ETIME;

		goto error_unlock_reset;

		}

	r = 0;

	}



error_unlock_reset:

	up_read(&adev->reset_domain->sem);

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

+0 −15
Original line number Diff line number Diff line
@@ -554,21 +554,6 @@ TRACE_EVENT(amdgpu_reset_reg_dumps, 
		      __entry->value)

);



TRACE_EVENT(amdgpu_runpm_reference_dumps,

	    TP_PROTO(uint32_t index, const char *func),

	    TP_ARGS(index, func),

	    TP_STRUCT__entry(

			     __field(uint32_t, index)

			     __string(func, func)

			     ),

	    TP_fast_assign(

			   __entry->index = index;

			   __assign_str(func);

			   ),

	    TP_printk("amdgpu runpm reference dump 0x%x: 0x%s\n",

		      __entry->index,

		      __get_str(func))

);

#undef AMDGPU_JOB_GET_TIMELINE_NAME

#endif

drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c

+13 −2
Original line number Diff line number Diff line
@@ -4195,9 +4195,10 @@ static u32 gfx_v9_4_3_get_cu_active_bitmap(struct amdgpu_device *adev, int xcc_i 
static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev,

				 struct amdgpu_cu_info *cu_info)

{

	int i, j, k, counter, xcc_id, active_cu_number = 0;

	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;

	int i, j, k, prev_counter, counter, xcc_id, active_cu_number = 0;

	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0, tmp;

	unsigned disable_masks[4 * 4];

	bool is_symmetric_cus;



	if (!adev || !cu_info)

		return -EINVAL;
@@ -4215,6 +4216,7 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 


	mutex_lock(&adev->grbm_idx_mutex);

	for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) {

		is_symmetric_cus = true;

		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {

			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {

				mask = 1;
@@ -4242,6 +4244,15 @@ static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, 
					ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));

				cu_info->ao_cu_bitmap[i][j] = ao_bitmap;

			}

			if (i && is_symmetric_cus && prev_counter != counter)

				is_symmetric_cus = false;

			prev_counter = counter;

		}

		if (is_symmetric_cus) {

			tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG);

			tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_RELAUNCH_DISABLE, 1);

			tmp = REG_SET_FIELD(tmp, CP_CPC_DEBUG, CPC_HARVESTING_DISPATCH_DISABLE, 1);

			WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_DEBUG, tmp);

		}

		gfx_v9_4_3_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff,

					    xcc_id);