Commit d6caeafa authored by Mario Limonciello's avatar Mario Limonciello Committed by Borislav Petkov (AMD)
Browse files

x86/amd_nb: Move SMN access code to a new amd_node driver 



SMN access was bolted into amd_nb mostly as convenience.  This has
limitations though that require incurring tech debt to keep it working.

Move SMN access to the newly introduced AMD Node driver.

Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Acked-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> # pdx86
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> # PMF, PMC
Link: https://lore.kernel.org/r/20241206161210.163701-11-yazen.ghannam@amd.com
parent 7dd57db4

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -1122,6 +1122,7 @@ S: Supported 
F:	drivers/i2c/busses/i2c-amd-asf-plat.c









AMD NODE DRIVER









M:	Mario Limonciello <mario.limonciello@amd.com>









M:	Yazen Ghannam <yazen.ghannam@amd.com>









L:	linux-kernel@vger.kernel.org









S:	Supported
































arch/x86/include/asm/amd_nb.h



+0
−3






























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Diff line







@@ -21,9 +21,6 @@ extern int amd_numa_init(void);







extern int amd_get_subcaches(int);









extern int amd_set_subcaches(int, unsigned long);



















int __must_check amd_smn_read(u16 node, u32 address, u32 *value);









int __must_check amd_smn_write(u16 node, u32 address, u32 value);



















struct amd_l3_cache {









	unsigned indices;









	u8	 subcaches[4];
































arch/x86/include/asm/amd_node.h



+3
−0






























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@@ -30,4 +30,7 @@ static inline u16 amd_num_nodes(void)







	return topology_amd_nodes_per_pkg() * topology_max_packages();









}



















int __must_check amd_smn_read(u16 node, u32 address, u32 *value);









int __must_check amd_smn_write(u16 node, u32 address, u32 value);



















#endif /*_ASM_X86_AMD_NODE_H_*/
























arch/x86/kernel/amd_nb.c



+0
−89






























Original line number
Diff line number
Diff line







@@ -15,9 +15,6 @@







#include <linux/pci_ids.h>









#include <asm/amd_nb.h>



















/* Protect the PCI config register pairs used for SMN. */









static DEFINE_MUTEX(smn_mutex);



















static u32 *flush_words;



















static const struct pci_device_id amd_nb_misc_ids[] = {








@@ -59,92 +56,6 @@ struct amd_northbridge *node_to_amd_nb(int node)







}









EXPORT_SYMBOL_GPL(node_to_amd_nb);



















/*









 * SMN accesses may fail in ways that are difficult to detect here in the called









 * functions amd_smn_read() and amd_smn_write(). Therefore, callers must do









 * their own checking based on what behavior they expect.









 *









 * For SMN reads, the returned value may be zero if the register is Read-as-Zero.









 * Or it may be a "PCI Error Response", e.g. all 0xFFs. The "PCI Error Response"









 * can be checked here, and a proper error code can be returned.









 *









 * But the Read-as-Zero response cannot be verified here. A value of 0 may be









 * correct in some cases, so callers must check that this correct is for the









 * register/fields they need.









 *









 * For SMN writes, success can be determined through a "write and read back"









 * However, this is not robust when done here.









 *









 * Possible issues:









 *









 * 1) Bits that are "Write-1-to-Clear". In this case, the read value should









 *    *not* match the write value.









 *









 * 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be









 *    known here.









 *









 * 3) Bits that are "Reserved / Set to 1". Ditto above.









 *









 * Callers of amd_smn_write() should do the "write and read back" check









 * themselves, if needed.









 *









 * For #1, they can see if their target bits got cleared.









 *









 * For #2 and #3, they can check if their target bits got set as intended.









 *









 * This matches what is done for RDMSR/WRMSR. As long as there's no #GP, then









 * the operation is considered a success, and the caller does their own









 * checking.









 */









static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)









{









	struct pci_dev *root;









	int err = -ENODEV;



















	if (node >= amd_northbridges.num)









		goto out;



















	root = node_to_amd_nb(node)->root;









	if (!root)









		goto out;



















	mutex_lock(&smn_mutex);



















	err = pci_write_config_dword(root, 0x60, address);









	if (err) {









		pr_warn("Error programming SMN address 0x%x.\n", address);









		goto out_unlock;









	}



















	err = (write ? pci_write_config_dword(root, 0x64, *value)









		     : pci_read_config_dword(root, 0x64, value));



















out_unlock:









	mutex_unlock(&smn_mutex);



















out:









	return err;









}



















int __must_check amd_smn_read(u16 node, u32 address, u32 *value)









{









	int err = __amd_smn_rw(node, address, value, false);



















	if (PCI_POSSIBLE_ERROR(*value)) {









		err = -ENODEV;









		*value = 0;









	}



















	return err;









}









EXPORT_SYMBOL_GPL(amd_smn_read);



















int __must_check amd_smn_write(u16 node, u32 address, u32 value)









{









	return __amd_smn_rw(node, address, &value, true);









}









EXPORT_SYMBOL_GPL(amd_smn_write);



















static int amd_cache_northbridges(void)









{









	struct amd_northbridge *nb;
































arch/x86/kernel/amd_node.c



+90
−0






























Original line number
Diff line number
Diff line







@@ -8,6 +8,7 @@







 * Author: Yazen Ghannam <Yazen.Ghannam@amd.com>









 */



















#include <asm/amd_nb.h>









#include <asm/amd_node.h>



















/*








@@ -88,3 +89,92 @@ struct pci_dev *amd_node_get_root(u16 node)







	pci_dbg(root, "is root for AMD node %u\n", node);









	return root;









}



















/* Protect the PCI config register pairs used for SMN. */









static DEFINE_MUTEX(smn_mutex);



















/*









 * SMN accesses may fail in ways that are difficult to detect here in the called









 * functions amd_smn_read() and amd_smn_write(). Therefore, callers must do









 * their own checking based on what behavior they expect.









 *









 * For SMN reads, the returned value may be zero if the register is Read-as-Zero.









 * Or it may be a "PCI Error Response", e.g. all 0xFFs. The "PCI Error Response"









 * can be checked here, and a proper error code can be returned.









 *









 * But the Read-as-Zero response cannot be verified here. A value of 0 may be









 * correct in some cases, so callers must check that this correct is for the









 * register/fields they need.









 *









 * For SMN writes, success can be determined through a "write and read back"









 * However, this is not robust when done here.









 *









 * Possible issues:









 *









 * 1) Bits that are "Write-1-to-Clear". In this case, the read value should









 *    *not* match the write value.









 *









 * 2) Bits that are "Read-as-Zero"/"Writes-Ignored". This information cannot be









 *    known here.









 *









 * 3) Bits that are "Reserved / Set to 1". Ditto above.









 *









 * Callers of amd_smn_write() should do the "write and read back" check









 * themselves, if needed.









 *









 * For #1, they can see if their target bits got cleared.









 *









 * For #2 and #3, they can check if their target bits got set as intended.









 *









 * This matches what is done for RDMSR/WRMSR. As long as there's no #GP, then









 * the operation is considered a success, and the caller does their own









 * checking.









 */









static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)









{









	struct pci_dev *root;









	int err = -ENODEV;



















	if (node >= amd_nb_num())









		goto out;



















	root = node_to_amd_nb(node)->root;









	if (!root)









		goto out;



















	mutex_lock(&smn_mutex);



















	err = pci_write_config_dword(root, 0x60, address);









	if (err) {









		pr_warn("Error programming SMN address 0x%x.\n", address);









		goto out_unlock;









	}



















	err = (write ? pci_write_config_dword(root, 0x64, *value)









		     : pci_read_config_dword(root, 0x64, value));



















out_unlock:









	mutex_unlock(&smn_mutex);



















out:









	return err;









}



















int __must_check amd_smn_read(u16 node, u32 address, u32 *value)









{









	int err = __amd_smn_rw(node, address, value, false);



















	if (PCI_POSSIBLE_ERROR(*value)) {









		err = -ENODEV;









		*value = 0;









	}



















	return err;









}









EXPORT_SYMBOL_GPL(amd_smn_read);



















int __must_check amd_smn_write(u16 node, u32 address, u32 value)









{









	return __amd_smn_rw(node, address, &value, true);









}









EXPORT_SYMBOL_GPL(amd_smn_write);