Commit d730905b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS updates from Thomas Bogendoerfer:

 - Support for Mobileye EyeQ6Lplus

 - Cleanups and fixes

* tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits)
  MIPS/mtd: Handle READY GPIO in generic NAND platform data
  MIPS/input: Move RB532 button to GPIO descriptors
  MIPS: validate DT bootargs before appending them
  MIPS: Alchemy: Remove unused forward declaration
  MAINTAINERS: Mobileye: Add EyeQ6Lplus files
  MIPS: config: add eyeq6lplus_defconfig
  MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
  MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
  clk: eyeq: Add Mobileye EyeQ6Lplus OLB
  clk: eyeq: Adjust PLL accuracy computation
  clk: eyeq: Skip post-divisor when computing PLL frequency
  pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
  pinctrl: eyeq5: Use match data
  reset: eyeq: Add Mobileye EyeQ6Lplus OLB
  MIPS: Add Mobileye EyeQ6Lplus support
  dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
  dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC
  MIPS: dts: loongson64g-package: Switch to Loongson UART driver
  mips: pci-mt7620: rework initialization procedure
  mips: pci-mt7620: add more register init values
  ...
parents a10e80be 15513eef

Documentation/devicetree/bindings/mips/mobileye.yaml

+5 −0
Original line number Diff line number Diff line
@@ -31,6 +31,11 @@ properties: 
          - enum:

              - mobileye,eyeq6h-epm6

          - const: mobileye,eyeq6h

      - description: Boards with Mobileye EyeQ6Lplus SoC

        items:

          - enum:

              - mobileye,eyeq6lplus-epm6

          - const: mobileye,eyeq6lplus



additionalProperties: true

Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml

+6 −1
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ properties: 
  clock-names:

    const: ref



  '#phy-cells':

    const: 1



patternProperties:

  '-pins?$':

    type: object
@@ -310,7 +313,7 @@ allOf: 
      properties:

        '#reset-cells': false



    # Only EyeQ5 has pinctrl in OLB.

    # Only EyeQ5 has pinctrl and PHY in OLB.

  - if:

      not:

        properties:
@@ -320,6 +323,8 @@ allOf: 
    then:

      patternProperties:

        '-pins?$': false

      properties:

        '#phy-cells': false



examples:

  - |

Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml

0 → 100644
+208 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq6lplus-olb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobileye EyeQ6Lplus SoC system controller



maintainers:

  - Benoît Monin <benoit.monin@bootlin.com>

  - Grégory Clement <gregory.clement@bootlin.com>

  - Théo Lebrun <theo.lebrun@bootlin.com>

  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>



description:

  OLB ("Other Logic Block") is a hardware block grouping smaller blocks.

  Clocks, resets, pinctrl are being handled from here. EyeQ6Lplus hosts

  a single instance providing 22 clocks, two reset domains and one bank

  of 32 pins.



properties:

  compatible:

    items:

      - const: mobileye,eyeq6lplus-olb

      - const: syscon



  reg:

    maxItems: 1



  '#reset-cells':

    description:

      First cell is reset domain index.

      Second cell is reset index inside that domain.

    const: 2



  '#clock-cells':

    const: 1



  clocks:

    maxItems: 1

    description:

      Input parent clock to all PLLs. Expected to be the main crystal.



  clock-names:

    const: ref



patternProperties:

  '-pins?$':

    type: object

    description: Pin muxing configuration.

    $ref: /schemas/pinctrl/pinmux-node.yaml#

    additionalProperties: false

    properties:

      pins: true

      function:

        enum: [gpio, timer0, timer1, uart_ssi, spi0, uart0, timer2, timer3,

               timer_ext0, spi1, timer_ext1, ext_ref_clk, mipi_ref_clk]

      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength: true

    required:

      - pins

      - function

    allOf:

      - if:

          properties:

            function:

              const: gpio

        then:

          properties:

            pins:

              items: # PA0 - PA31

                pattern: '^(PA[1,2]?[0-9]|PA3[0,1])$'

      - if:

          properties:

            function:

              const: timer0

        then:

          properties:

            pins:

              items:

                enum: [PA0, PA1]

      - if:

          properties:

            function:

              const: timer1

        then:

          properties:

            pins:

              items:

                enum: [PA2, PA3]

      - if:

          properties:

            function:

              const: uart_ssi

        then:

          properties:

            pins:

              items:

                enum: [PA4, PA5]

      - if:

          properties:

            function:

              const: spi0

        then:

          properties:

            pins:

              items:

                enum: [PA6, PA7, PA8, PA9, PA10]

      - if:

          properties:

            function:

              const: uart0

        then:

          properties:

            pins:

              items:

                enum: [PA11, PA12]

      - if:

          properties:

            function:

              const: timer2

        then:

          properties:

            pins:

              items:

                enum: [PA13, PA14]

      - if:

          properties:

            function:

              const: timer3

        then:

          properties:

            pins:

              items:

                enum: [PA15, PA16]

      - if:

          properties:

            function:

              const: timer_ext0

        then:

          properties:

            pins:

              items:

                enum: [PA17, PA18, PA19, PA20]

      - if:

          properties:

            function:

              const: spi1

        then:

          properties:

            pins:

              items:

                enum: [PA21, PA22, PA23, PA24, PA25]

      - if:

          properties:

            function:

              const: timer_ext1

        then:

          properties:

            pins:

              items:

                enum: [PA26, PA27, PA28, PA29]

      - if:

          properties:

            function:

              const: ext_ref_clk

        then:

          properties:

            pins:

              items:

                enum: [PA30]

      - if:

          properties:

            function:

              const: mipi_ref_clk

        then:

          properties:

            pins:

              items:

                enum: [PA31]



required:

  - compatible

  - reg

  - '#clock-cells'

  - clocks

  - clock-names

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    soc {

      #address-cells = <2>;

      #size-cells = <2>;



      system-controller@e8400000 {

        compatible = "mobileye,eyeq6lplus-olb", "syscon";

        reg = <0 0xe8400000 0x0 0x80000>;

        #reset-cells = <2>;

        #clock-cells = <1>;

        clocks = <&xtal>;

        clock-names = "ref";

      };

    };

MAINTAINERS

+3 −1
Original line number Diff line number Diff line
@@ -17913,6 +17913,7 @@ F: drivers/media/dvb-frontends/mn88473* 








MOBILEYE MIPS SOCS









M:	Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>









M:	Benoît Monin <benoit.monin@bootlin.com>









M:	Gregory CLEMENT <gregory.clement@bootlin.com>









M:	Théo Lebrun <theo.lebrun@bootlin.com>









L:	linux-mips@vger.kernel.org








@@ -17920,12 +17921,13 @@ S:	Maintained







F:	Documentation/devicetree/bindings/mips/mobileye.yaml









F:	Documentation/devicetree/bindings/soc/mobileye/









F:	arch/mips/boot/dts/mobileye/









F:	arch/mips/configs/eyeq5_defconfig









F:	arch/mips/configs/eyeq*_defconfig









F:	arch/mips/mobileye/board-epm5.its.S









F:	drivers/clk/clk-eyeq.c









F:	drivers/pinctrl/pinctrl-eyeq5.c









F:	drivers/reset/reset-eyeq.c









F:	include/dt-bindings/clock/mobileye,eyeq5-clk.h









F:	include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h

















MODULE SUPPORT









M:	Luis Chamberlain <mcgrof@kernel.org>

























arch/mips/boot/dts/econet/en751221.dtsi



+114
−0






























Original line number
Diff line number
Diff line









// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)









/dts-v1/;



















#include <dt-bindings/clock/econet,en751221-scu.h>



















/ {









	compatible = "econet,en751221";









	#address-cells = <1>;








@@ -30,6 +32,30 @@ cpuintc: interrupt-controller {







		#interrupt-cells = <1>;









	};



















	chip_scu: syscon@1fa20000 {









		compatible = "econet,en751221-chip-scu", "syscon";









		reg = <0x1fa20000 0x388>;









	};



















	pcie_phy1: pcie-phy@1fac0000 {









		compatible = "econet,en751221-pcie-gen2";









		reg = <0x1fac0000 0x1000>;









		#phy-cells = <0>;









	};



















	pcie_phy0: pcie-phy@1faf2000 {









		compatible = "econet,en751221-pcie-gen1";









		reg = <0x1faf2000 0x1000>;









		#phy-cells = <0>;









	};



















	scuclk: clock-controller@1fb00000 {









		compatible = "econet,en751221-scu";









		reg = <0x1fb00000 0x970>;









		#clock-cells = <1>;









		#reset-cells = <1>;









	};



















	intc: interrupt-controller@1fb40000 {









		compatible = "econet,en751221-intc";









		reg = <0x1fb40000 0x100>;








@@ -41,6 +67,94 @@ intc: interrupt-controller@1fb40000 {







		econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;









	};



















	pciecfg: pciecfg@1fb80000 {









		compatible = "mediatek,generic-pciecfg", "syscon";









		reg = <0x1fb80000 0x1000>;









	};



















	pcie0: pcie@1fb81000 {









		compatible = "econet,en7528-pcie";









		device_type = "pci";









		reg = <0x1fb81000 0x1000>;









		reg-names = "port0";









		linux,pci-domain = <0>;









		#address-cells = <3>;









		#size-cells = <2>;









		interrupt-parent = <&intc>;









		interrupts = <23>;









		interrupt-names = "pcie_irq";









		clocks = <&scuclk EN751221_CLK_PCIE>;









		clock-names = "sys_ck0";









		phys = <&pcie_phy0>;









		phy-names = "pcie-phy0";









		bus-range = <0x00 0xff>;









		ranges = <0x01000000 0 0x00000000 0x1f600000 0 0x00008000>,









			 <0x82000000 0 0x20000000 0x20000000 0 0x08000000>;









		status = "disabled";



















		#interrupt-cells = <1>;









		interrupt-map-mask = <0 0 0 7>;









		interrupt-map = <0 0 0 1 &pcie_intc0 0>,









				<0 0 0 2 &pcie_intc0 1>,









				<0 0 0 3 &pcie_intc0 2>,









				<0 0 0 4 &pcie_intc0 3>;



















		pcie_intc0: interrupt-controller {









			interrupt-controller;









			#address-cells = <0>;









			#interrupt-cells = <1>;









		};



















		slot0: pcie@0,0 {









			reg = <0x0000 0 0 0 0>;









			device_type = "pci";









			#address-cells = <3>;









			#size-cells = <2>;









			ranges;









		};









	};



















	pcie1: pcie@1fb83000 {









		compatible = "econet,en7528-pcie";









		device_type = "pci";









		reg = <0x1fb83000 0x1000>;









		reg-names = "port1";









		linux,pci-domain = <1>;









		#address-cells = <3>;









		#size-cells = <2>;









		interrupt-parent = <&intc>;









		interrupts = <24>;









		interrupt-names = "pcie_irq";









		clocks = <&scuclk EN751221_CLK_PCIE>;









		clock-names = "sys_ck1";









		phys = <&pcie_phy1>;









		phy-names = "pcie-phy1";









		bus-range = <0x00 0xff>;









		ranges = <0x81000000 0 0x00000000 0x1f608000 0 0x00008000>,









			 <0x82000000 0 0x28000000 0x28000000 0 0x08000000>;









		status = "disabled";



















		#interrupt-cells = <1>;









		interrupt-map-mask = <0 0 0 7>;









		interrupt-map = <0 0 0 1 &pcie_intc1 0>,









				<0 0 0 2 &pcie_intc1 1>,









				<0 0 0 3 &pcie_intc1 2>,









				<0 0 0 4 &pcie_intc1 3>;



















		pcie_intc1: interrupt-controller {









			interrupt-controller;









			#address-cells = <0>;









			#interrupt-cells = <1>;









		};



















		slot1: pcie@1,0 {









			reg = <0x0800 0 0 0 0>;









			#address-cells = <3>;









			#size-cells = <2>;









			ranges;









		};









	};



















	uart: serial@1fbf0000 {









		compatible = "ns16550";









		reg = <0x1fbf0000 0x30>;