Commit d77037bb authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: s/disable_lp_wm/disable_cxsr/ 



The ilk+ disable_lp_wm boolean has the exact same role as
disable_cxsr for gmch platforms. The documentation also
still talks about CxSR on ilk+ even theough the way you
control it has now change to involve toggling the LP watermarks.
Get rid of disable_lp_wm and just use disable_cxsr for ilk+
as well.

TODO: Unify even more to not have any gmch vs. ilk+
      details in high level modeset code...

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240916162413.8555-7-ville.syrjala@linux.intel.com


Reviewed-by: default avatarVinod Govindapillai <vinod.govindapillai@intel.com>
parent 7572d3f7

drivers/gpu/drm/i915/display/i9xx_wm.c

+1 −1
Original line number Diff line number Diff line
@@ -3397,7 +3397,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 
	dev_priv->display.wm.hw = *results;

}



bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)

bool ilk_disable_cxsr(struct drm_i915_private *dev_priv)

{

	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);

}

drivers/gpu/drm/i915/display/i9xx_wm.h

+2 −2
Original line number Diff line number Diff line
@@ -13,12 +13,12 @@ struct intel_crtc_state; 
struct intel_plane_state;



#ifdef I915

bool ilk_disable_lp_wm(struct drm_i915_private *i915);

bool ilk_disable_cxsr(struct drm_i915_private *i915);

void ilk_wm_sanitize(struct drm_i915_private *i915);

bool intel_set_memory_cxsr(struct drm_i915_private *i915, bool enable);

void i9xx_wm_init(struct drm_i915_private *i915);

#else

static inline bool ilk_disable_lp_wm(struct drm_i915_private *i915)

static inline bool ilk_disable_cxsr(struct drm_i915_private *i915)

{

	return false;

}

drivers/gpu/drm/i915/display/intel_atomic.c

+0 −1
Original line number Diff line number Diff line
@@ -266,7 +266,6 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) 
	crtc_state->update_pipe = false;

	crtc_state->update_m_n = false;

	crtc_state->update_lrr = false;

	crtc_state->disable_lp_wm = false;

	crtc_state->disable_cxsr = false;

	crtc_state->update_wm_pre = false;

	crtc_state->update_wm_post = false;

drivers/gpu/drm/i915/display/intel_atomic_plane.c

+5 −5
Original line number Diff line number Diff line
@@ -471,7 +471,7 @@ static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state 
	return old_ctl != new_ctl;

}



static bool ilk_must_disable_lp_wm(const struct intel_crtc_state *new_crtc_state,

static bool ilk_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,

				  const struct intel_plane_state *old_plane_state,

				  const struct intel_plane_state *new_plane_state)

{
@@ -588,8 +588,8 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr 
		new_crtc_state->disable_cxsr = true;



	if ((IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) &&

	    ilk_must_disable_lp_wm(new_crtc_state, old_plane_state, new_plane_state))

		new_crtc_state->disable_lp_wm = true;

	    ilk_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))

		new_crtc_state->disable_cxsr = true;



	if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {

		new_crtc_state->do_async_flip = true;

drivers/gpu/drm/i915/display/intel_display.c

+2 −2
Original line number Diff line number Diff line
@@ -1324,8 +1324,8 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, 
	 *

	 * WaCxSRDisabledForSpriteScaling:ivb

	 */

	if (old_crtc_state->hw.active &&

	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))

	if (!HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&

	    new_crtc_state->disable_cxsr && ilk_disable_cxsr(dev_priv))

		intel_crtc_wait_for_next_vblank(crtc);



	/*