Commit d77ca6c2 authored by Dan Williams's avatar Dan Williams Committed by Dave Jiang
Browse files

cxl: Introduce to_{ram,pmem}_{res,perf}() helpers 



In preparation for consolidating all DPA partition information into an
array of DPA metadata, introduce helpers that hide the layout of the
current data. I.e. make the eventual replacement of ->ram_res,
->pmem_res, ->ram_perf, and ->pmem_perf with a new DPA metadata array a
no-op for code paths that consume that information, and reduce the noise
of follow-on patches.

The end goal is to consolidate all DPA information in 'struct
cxl_dev_state', but for now the helpers just make it appear that all DPA
metadata is relative to @cxlds.

As the conversion to generic partition metadata walking is completed,
these helpers will naturally be eliminated, or reduced in scope.

Cc: Alejandro Lucero <alucerop@amd.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Reviewed-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarFan Ni <fan.ni@samsung.com>
Tested-by: default avatarAlejandro Lucero <alucerop@amd.com>
Link: https://patch.msgid.link/173864305238.668823.16553986866633608541.stgit@dwillia2-xfh.jf.intel.com


Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 188e9529

drivers/cxl/core/cdat.c

+45 −26
Original line number Diff line number Diff line
@@ -258,27 +258,36 @@ static void update_perf_entry(struct device *dev, struct dsmas_entry *dent, 
static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,

				     struct xarray *dsmas_xa)

{

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);

	struct device *dev = cxlds->dev;

	struct range pmem_range = {

		.start = cxlds->pmem_res.start,

		.end = cxlds->pmem_res.end,

	};

	struct range ram_range = {

		.start = cxlds->ram_res.start,

		.end = cxlds->ram_res.end,

	};

	struct dsmas_entry *dent;

	unsigned long index;

	const struct resource *partition[] = {

		to_ram_res(cxlds),

		to_pmem_res(cxlds),

	};

	struct cxl_dpa_perf *perf[] = {

		to_ram_perf(cxlds),

		to_pmem_perf(cxlds),

	};



	xa_for_each(dsmas_xa, index, dent) {

		if (resource_size(&cxlds->ram_res) &&

		    range_contains(&ram_range, &dent->dpa_range))

			update_perf_entry(dev, dent, &mds->ram_perf);

		else if (resource_size(&cxlds->pmem_res) &&

			 range_contains(&pmem_range, &dent->dpa_range))

			update_perf_entry(dev, dent, &mds->pmem_perf);

		else

		bool found = false;



		for (int i = 0; i < ARRAY_SIZE(partition); i++) {

			const struct resource *res = partition[i];

			struct range range = {

				.start = res->start,

				.end = res->end,

			};



			if (range_contains(&range, &dent->dpa_range)) {

				update_perf_entry(dev, dent, perf[i]);

				found = true;

				break;

			}

		}



		if (!found)

			dev_dbg(dev, "no partition for dsmas dpa: %pra\n",

				&dent->dpa_range);

	}
@@ -304,6 +313,9 @@ static int match_cxlrd_qos_class(struct device *dev, void *data) 


static void reset_dpa_perf(struct cxl_dpa_perf *dpa_perf)

{

	if (!dpa_perf)

		return;



	*dpa_perf = (struct cxl_dpa_perf) {

		.qos_class = CXL_QOS_CLASS_INVALID,

	};
@@ -312,6 +324,9 @@ static void reset_dpa_perf(struct cxl_dpa_perf *dpa_perf) 
static bool cxl_qos_match(struct cxl_port *root_port,

			  struct cxl_dpa_perf *dpa_perf)

{

	if (!dpa_perf)

		return false;



	if (dpa_perf->qos_class == CXL_QOS_CLASS_INVALID)

		return false;
@@ -346,7 +361,8 @@ static int match_cxlrd_hb(struct device *dev, void *data) 
static int cxl_qos_class_verify(struct cxl_memdev *cxlmd)

{

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);

	struct cxl_dpa_perf *ram_perf = to_ram_perf(cxlds),

			    *pmem_perf = to_pmem_perf(cxlds);

	struct cxl_port *root_port;

	int rc;
@@ -359,17 +375,17 @@ static int cxl_qos_class_verify(struct cxl_memdev *cxlmd) 
	root_port = &cxl_root->port;



	/* Check that the QTG IDs are all sane between end device and root decoders */

	if (!cxl_qos_match(root_port, &mds->ram_perf))

		reset_dpa_perf(&mds->ram_perf);

	if (!cxl_qos_match(root_port, &mds->pmem_perf))

		reset_dpa_perf(&mds->pmem_perf);

	if (!cxl_qos_match(root_port, ram_perf))

		reset_dpa_perf(ram_perf);

	if (!cxl_qos_match(root_port, pmem_perf))

		reset_dpa_perf(pmem_perf);



	/* Check to make sure that the device's host bridge is under a root decoder */

	rc = device_for_each_child(&root_port->dev,

				   cxlmd->endpoint->host_bridge, match_cxlrd_hb);

	if (!rc) {

		reset_dpa_perf(&mds->ram_perf);

		reset_dpa_perf(&mds->pmem_perf);

		reset_dpa_perf(ram_perf);

		reset_dpa_perf(pmem_perf);

	}



	return rc;
@@ -574,20 +590,23 @@ static struct cxl_dpa_perf *cxled_get_dpa_perf(struct cxl_endpoint_decoder *cxle 
					       enum cxl_decoder_mode mode)

{

	struct cxl_memdev *cxlmd = cxled_to_memdev(cxled);

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	struct cxl_dpa_perf *perf;



	switch (mode) {

	case CXL_DECODER_RAM:

		perf = &mds->ram_perf;

		perf = to_ram_perf(cxlds);

		break;

	case CXL_DECODER_PMEM:

		perf = &mds->pmem_perf;

		perf = to_pmem_perf(cxlds);

		break;

	default:

		return ERR_PTR(-EINVAL);

	}



	if (!perf)

		return ERR_PTR(-EINVAL);



	if (!dpa_perf_contains(perf, cxled->dpa_res))

		return ERR_PTR(-EINVAL);

drivers/cxl/core/hdm.c

+14 −12
Original line number Diff line number Diff line
@@ -327,9 +327,9 @@ static int __cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled, 
	cxled->dpa_res = res;

	cxled->skip = skipped;



	if (resource_contains(&cxlds->pmem_res, res))

	if (resource_contains(to_pmem_res(cxlds), res))

		cxled->mode = CXL_DECODER_PMEM;

	else if (resource_contains(&cxlds->ram_res, res))

	else if (resource_contains(to_ram_res(cxlds), res))

		cxled->mode = CXL_DECODER_RAM;

	else {

		dev_warn(dev, "decoder%d.%d: %pr does not map any partition\n",
@@ -442,11 +442,11 @@ int cxl_dpa_set_mode(struct cxl_endpoint_decoder *cxled, 
	 * Only allow modes that are supported by the current partition

	 * configuration

	 */

	if (mode == CXL_DECODER_PMEM && !resource_size(&cxlds->pmem_res)) {

	if (mode == CXL_DECODER_PMEM && !cxl_pmem_size(cxlds)) {

		dev_dbg(dev, "no available pmem capacity\n");

		return -ENXIO;

	}

	if (mode == CXL_DECODER_RAM && !resource_size(&cxlds->ram_res)) {

	if (mode == CXL_DECODER_RAM && !cxl_ram_size(cxlds)) {

		dev_dbg(dev, "no available ram capacity\n");

		return -ENXIO;

	}
@@ -464,6 +464,8 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) 
	struct device *dev = &cxled->cxld.dev;

	resource_size_t start, avail, skip;

	struct resource *p, *last;

	const struct resource *ram_res = to_ram_res(cxlds);

	const struct resource *pmem_res = to_pmem_res(cxlds);

	int rc;



	down_write(&cxl_dpa_rwsem);
@@ -480,37 +482,37 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size) 
		goto out;

	}



	for (p = cxlds->ram_res.child, last = NULL; p; p = p->sibling)

	for (p = ram_res->child, last = NULL; p; p = p->sibling)

		last = p;

	if (last)

		free_ram_start = last->end + 1;

	else

		free_ram_start = cxlds->ram_res.start;

		free_ram_start = ram_res->start;



	for (p = cxlds->pmem_res.child, last = NULL; p; p = p->sibling)

	for (p = pmem_res->child, last = NULL; p; p = p->sibling)

		last = p;

	if (last)

		free_pmem_start = last->end + 1;

	else

		free_pmem_start = cxlds->pmem_res.start;

		free_pmem_start = pmem_res->start;



	if (cxled->mode == CXL_DECODER_RAM) {

		start = free_ram_start;

		avail = cxlds->ram_res.end - start + 1;

		avail = ram_res->end - start + 1;

		skip = 0;

	} else if (cxled->mode == CXL_DECODER_PMEM) {

		resource_size_t skip_start, skip_end;



		start = free_pmem_start;

		avail = cxlds->pmem_res.end - start + 1;

		avail = pmem_res->end - start + 1;

		skip_start = free_ram_start;



		/*

		 * If some pmem is already allocated, then that allocation

		 * already handled the skip.

		 */

		if (cxlds->pmem_res.child &&

		    skip_start == cxlds->pmem_res.child->start)

		if (pmem_res->child &&

		    skip_start == pmem_res->child->start)

			skip_end = skip_start - 1;

		else

			skip_end = start - 1;

drivers/cxl/core/mbox.c

+10 −8
Original line number Diff line number Diff line
@@ -1270,24 +1270,26 @@ static int add_dpa_res(struct device *dev, struct resource *parent, 
int cxl_mem_create_range_info(struct cxl_memdev_state *mds)

{

	struct cxl_dev_state *cxlds = &mds->cxlds;

	struct resource *ram_res = to_ram_res(cxlds);

	struct resource *pmem_res = to_pmem_res(cxlds);

	struct device *dev = cxlds->dev;

	int rc;



	if (!cxlds->media_ready) {

		cxlds->dpa_res = DEFINE_RES_MEM(0, 0);

		cxlds->ram_res = DEFINE_RES_MEM(0, 0);

		cxlds->pmem_res = DEFINE_RES_MEM(0, 0);

		*ram_res = DEFINE_RES_MEM(0, 0);

		*pmem_res = DEFINE_RES_MEM(0, 0);

		return 0;

	}



	cxlds->dpa_res = DEFINE_RES_MEM(0, mds->total_bytes);



	if (mds->partition_align_bytes == 0) {

		rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->ram_res, 0,

		rc = add_dpa_res(dev, &cxlds->dpa_res, ram_res, 0,

				 mds->volatile_only_bytes, "ram");

		if (rc)

			return rc;

		return add_dpa_res(dev, &cxlds->dpa_res, &cxlds->pmem_res,

		return add_dpa_res(dev, &cxlds->dpa_res, pmem_res,

				   mds->volatile_only_bytes,

				   mds->persistent_only_bytes, "pmem");

	}
@@ -1298,11 +1300,11 @@ int cxl_mem_create_range_info(struct cxl_memdev_state *mds) 
		return rc;

	}



	rc = add_dpa_res(dev, &cxlds->dpa_res, &cxlds->ram_res, 0,

	rc = add_dpa_res(dev, &cxlds->dpa_res, ram_res, 0,

			 mds->active_volatile_bytes, "ram");

	if (rc)

		return rc;

	return add_dpa_res(dev, &cxlds->dpa_res, &cxlds->pmem_res,

	return add_dpa_res(dev, &cxlds->dpa_res, pmem_res,

			   mds->active_volatile_bytes,

			   mds->active_persistent_bytes, "pmem");

}
@@ -1450,8 +1452,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev) 
	mds->cxlds.reg_map.host = dev;

	mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;

	mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;

	mds->ram_perf.qos_class = CXL_QOS_CLASS_INVALID;

	mds->pmem_perf.qos_class = CXL_QOS_CLASS_INVALID;

	to_ram_perf(&mds->cxlds)->qos_class = CXL_QOS_CLASS_INVALID;

	to_pmem_perf(&mds->cxlds)->qos_class = CXL_QOS_CLASS_INVALID;



	return mds;

}

drivers/cxl/core/memdev.c

+22 −20
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr, 
{

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	unsigned long long len = resource_size(&cxlds->ram_res);

	unsigned long long len = resource_size(to_ram_res(cxlds));



	return sysfs_emit(buf, "%#llx\n", len);

}
@@ -93,7 +93,7 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, 
{

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	unsigned long long len = resource_size(&cxlds->pmem_res);

	unsigned long long len = cxl_pmem_size(cxlds);



	return sysfs_emit(buf, "%#llx\n", len);

}
@@ -198,16 +198,20 @@ static int cxl_get_poison_by_memdev(struct cxl_memdev *cxlmd) 
	int rc = 0;



	/* CXL 3.0 Spec 8.2.9.8.4.1 Separate pmem and ram poison requests */

	if (resource_size(&cxlds->pmem_res)) {

		offset = cxlds->pmem_res.start;

		length = resource_size(&cxlds->pmem_res);

	if (cxl_pmem_size(cxlds)) {

		const struct resource *res = to_pmem_res(cxlds);



		offset = res->start;

		length = resource_size(res);

		rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);

		if (rc)

			return rc;

	}

	if (resource_size(&cxlds->ram_res)) {

		offset = cxlds->ram_res.start;

		length = resource_size(&cxlds->ram_res);

	if (cxl_ram_size(cxlds)) {

		const struct resource *res = to_ram_res(cxlds);



		offset = res->start;

		length = resource_size(res);

		rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);

		/*

		 * Invalid Physical Address is not an error for
@@ -409,9 +413,8 @@ static ssize_t pmem_qos_class_show(struct device *dev, 
{

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);



	return sysfs_emit(buf, "%d\n", mds->pmem_perf.qos_class);

	return sysfs_emit(buf, "%d\n", to_pmem_perf(cxlds)->qos_class);

}



static struct device_attribute dev_attr_pmem_qos_class =
@@ -428,9 +431,8 @@ static ssize_t ram_qos_class_show(struct device *dev, 
{

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_dev_state *cxlds = cxlmd->cxlds;

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds);



	return sysfs_emit(buf, "%d\n", mds->ram_perf.qos_class);

	return sysfs_emit(buf, "%d\n", to_ram_perf(cxlds)->qos_class);

}



static struct device_attribute dev_attr_ram_qos_class =
@@ -466,10 +468,10 @@ static umode_t cxl_ram_visible(struct kobject *kobj, struct attribute *a, int n) 
{

	struct device *dev = kobj_to_dev(kobj);

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);

	struct cxl_dpa_perf *perf = to_ram_perf(cxlmd->cxlds);



	if (a == &dev_attr_ram_qos_class.attr)

		if (mds->ram_perf.qos_class == CXL_QOS_CLASS_INVALID)

	if (a == &dev_attr_ram_qos_class.attr &&

	    (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))

		return 0;



	return a->mode;
@@ -485,10 +487,10 @@ static umode_t cxl_pmem_visible(struct kobject *kobj, struct attribute *a, int n 
{

	struct device *dev = kobj_to_dev(kobj);

	struct cxl_memdev *cxlmd = to_cxl_memdev(dev);

	struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlmd->cxlds);

	struct cxl_dpa_perf *perf = to_pmem_perf(cxlmd->cxlds);



	if (a == &dev_attr_pmem_qos_class.attr)

		if (mds->pmem_perf.qos_class == CXL_QOS_CLASS_INVALID)

	if (a == &dev_attr_pmem_qos_class.attr &&

	    (!perf || perf->qos_class == CXL_QOS_CLASS_INVALID))

		return 0;



	return a->mode;

drivers/cxl/core/region.c

+6 −4
Original line number Diff line number Diff line
@@ -2701,7 +2701,7 @@ static int cxl_get_poison_unmapped(struct cxl_memdev *cxlmd, 


	if (ctx->mode == CXL_DECODER_RAM) {

		offset = ctx->offset;

		length = resource_size(&cxlds->ram_res) - offset;

		length = cxl_ram_size(cxlds) - offset;

		rc = cxl_mem_get_poison(cxlmd, offset, length, NULL);

		if (rc == -EFAULT)

			rc = 0;
@@ -2713,9 +2713,11 @@ static int cxl_get_poison_unmapped(struct cxl_memdev *cxlmd, 
		length = resource_size(&cxlds->dpa_res) - offset;

		if (!length)

			return 0;

	} else if (resource_size(&cxlds->pmem_res)) {

		offset = cxlds->pmem_res.start;

		length = resource_size(&cxlds->pmem_res);

	} else if (cxl_pmem_size(cxlds)) {

		const struct resource *res = to_pmem_res(cxlds);



		offset = res->start;

		length = resource_size(res);

	} else {

		return 0;

	}