Commit d7999f5e authored by Arkadiusz Kubalewski's avatar Arkadiusz Kubalewski Committed by David S. Miller
Browse files

ice: implement dpll interface to control cgu 



Control over clock generation unit is required for further development
of Synchronous Ethernet feature. Interface provides ability to obtain
current state of a dpll, its sources and outputs which are pins, and
allows their configuration.

Co-developed-by: default avatarMilena Olech <milena.olech@intel.com>
Signed-off-by: default avatarMilena Olech <milena.olech@intel.com>
Co-developed-by: default avatarMichal Michalik <michal.michalik@intel.com>
Signed-off-by: default avatarMichal Michalik <michal.michalik@intel.com>
Signed-off-by: default avatarArkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: default avatarVadim Fedorenko <vadim.fedorenko@linux.dev>
Signed-off-by: default avatarJiri Pirko <jiri@nvidia.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8a3a565f

drivers/net/ethernet/intel/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -284,6 +284,7 @@ config ICE 
	select DIMLIB

	select NET_DEVLINK

	select PLDMFW

	select DPLL

	help

	  This driver supports Intel(R) Ethernet Connection E800 Series of

	  devices.  For more information on how to identify your adapter, go

drivers/net/ethernet/intel/ice/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -34,7 +34,8 @@ ice-y := ice_main.o \ 
	 ice_lag.o	\

	 ice_ethtool.o  \

	 ice_repr.o	\

	 ice_tc_lib.o

	 ice_tc_lib.o	\

	 ice_dpll.o

ice-$(CONFIG_PCI_IOV) +=	\

	ice_sriov.o		\

	ice_virtchnl.o		\

drivers/net/ethernet/intel/ice/ice.h

+3 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#include "ice_vsi_vlan_ops.h"

#include "ice_gnss.h"

#include "ice_irq.h"

#include "ice_dpll.h"



#define ICE_BAR0		0

#define ICE_REQ_DESC_MULTIPLE	32
@@ -510,6 +511,7 @@ enum ice_pf_flags { 
	ICE_FLAG_UNPLUG_AUX_DEV,

	ICE_FLAG_MTU_CHANGED,

	ICE_FLAG_GNSS,			/* GNSS successfully initialized */

	ICE_FLAG_DPLL,			/* SyncE/PTP dplls initialized */

	ICE_PF_FLAGS_NBITS		/* must be last */

};
@@ -642,6 +644,7 @@ struct ice_pf { 
#define ICE_VF_AGG_NODE_ID_START	65

#define ICE_MAX_VF_AGG_NODES		32

	struct ice_agg_node vf_agg_node[ICE_MAX_VF_AGG_NODES];

	struct ice_dplls dplls;

};



extern struct workqueue_struct *ice_lag_wq;

drivers/net/ethernet/intel/ice/ice_dpll.c

0 → 100644
+1904 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/intel/ice/ice_dpll.h

0 → 100644
+104 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (C) 2022, Intel Corporation. */



#ifndef _ICE_DPLL_H_

#define _ICE_DPLL_H_



#include "ice.h"



#define ICE_DPLL_PRIO_MAX	0xF

#define ICE_DPLL_RCLK_NUM_MAX	4



/** ice_dpll_pin - store info about pins

 * @pin: dpll pin structure

 * @pf: pointer to pf, which has registered the dpll_pin

 * @idx: ice pin private idx

 * @num_parents: hols number of parent pins

 * @parent_idx: hold indexes of parent pins

 * @flags: pin flags returned from HW

 * @state: state of a pin

 * @prop: pin properties

 * @freq: current frequency of a pin

 */

struct ice_dpll_pin {

	struct dpll_pin *pin;

	struct ice_pf *pf;

	u8 idx;

	u8 num_parents;

	u8 parent_idx[ICE_DPLL_RCLK_NUM_MAX];

	u8 flags[ICE_DPLL_RCLK_NUM_MAX];

	u8 state[ICE_DPLL_RCLK_NUM_MAX];

	struct dpll_pin_properties prop;

	u32 freq;

};



/** ice_dpll - store info required for DPLL control

 * @dpll: pointer to dpll dev

 * @pf: pointer to pf, which has registered the dpll_device

 * @dpll_idx: index of dpll on the NIC

 * @input_idx: currently selected input index

 * @prev_input_idx: previously selected input index

 * @ref_state: state of dpll reference signals

 * @eec_mode: eec_mode dpll is configured for

 * @phase_shift: phase shift delay of a dpll

 * @input_prio: priorities of each input

 * @dpll_state: current dpll sync state

 * @prev_dpll_state: last dpll sync state

 * @active_input: pointer to active input pin

 * @prev_input: pointer to previous active input pin

 */

struct ice_dpll {

	struct dpll_device *dpll;

	struct ice_pf *pf;

	u8 dpll_idx;

	u8 input_idx;

	u8 prev_input_idx;

	u8 ref_state;

	u8 eec_mode;

	s64 phase_shift;

	u8 *input_prio;

	enum dpll_lock_status dpll_state;

	enum dpll_lock_status prev_dpll_state;

	enum dpll_mode mode;

	struct dpll_pin *active_input;

	struct dpll_pin *prev_input;

};



/** ice_dplls - store info required for CCU (clock controlling unit)

 * @kworker: periodic worker

 * @work: periodic work

 * @lock: locks access to configuration of a dpll

 * @eec: pointer to EEC dpll dev

 * @pps: pointer to PPS dpll dev

 * @inputs: input pins pointer

 * @outputs: output pins pointer

 * @rclk: recovered pins pointer

 * @num_inputs: number of input pins available on dpll

 * @num_outputs: number of output pins available on dpll

 * @cgu_state_acq_err_num: number of errors returned during periodic work

 * @base_rclk_idx: idx of first pin used for clock revocery pins

 * @clock_id: clock_id of dplls

 */

struct ice_dplls {

	struct kthread_worker *kworker;

	struct kthread_delayed_work work;

	struct mutex lock;

	struct ice_dpll eec;

	struct ice_dpll pps;

	struct ice_dpll_pin *inputs;

	struct ice_dpll_pin *outputs;

	struct ice_dpll_pin rclk;

	u8 num_inputs;

	u8 num_outputs;

	int cgu_state_acq_err_num;

	u8 base_rclk_idx;

	u64 clock_id;

	s32 input_phase_adj_max;

	s32 output_phase_adj_max;

};



void ice_dpll_init(struct ice_pf *pf);



void ice_dpll_deinit(struct ice_pf *pf);



#endif