Commit d7a5aa4b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-tools-fixes-for-v6.11-2024-08-15' of... 

Merge tag 'perf-tools-fixes-for-v6.11-2024-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools fixes from Namhyung Kim:
 "The usual header file sync-ups and one more build fix:

   - Add README file to explain why we copy the headers

   - Sync UAPI and other header files with kernel source

   - Fix build on MIPS 32-bit"

* tag 'perf-tools-fixes-for-v6.11-2024-08-15' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools:
  perf daemon: Fix the build on 32-bit architectures
  tools/include: Sync arm64 headers with the kernel sources
  tools/include: Sync x86 headers with the kernel sources
  tools/include: Sync filesystem headers with the kernel sources
  tools/include: Sync network socket headers with the kernel sources
  tools/include: Sync uapi/asm-generic/unistd.h with the kernel sources
  tools/include: Sync uapi/sound/asound.h with the kernel sources
  tools/include: Sync uapi/linux/perf.h with the kernel sources
  tools/include: Sync uapi/linux/kvm.h with the kernel sources
  tools/include: Sync uapi/drm/i915_drm.h with the kernel sources
  perf tools: Add tools/include/uapi/README
parents e724918b 4bbe6002

tools/arch/arm64/include/asm/cputype.h

+10 −0
Original line number Diff line number Diff line
@@ -86,9 +86,14 @@ 
#define ARM_CPU_PART_CORTEX_X2		0xD48

#define ARM_CPU_PART_NEOVERSE_N2	0xD49

#define ARM_CPU_PART_CORTEX_A78C	0xD4B

#define ARM_CPU_PART_CORTEX_X1C		0xD4C

#define ARM_CPU_PART_CORTEX_X3		0xD4E

#define ARM_CPU_PART_NEOVERSE_V2	0xD4F

#define ARM_CPU_PART_CORTEX_A720	0xD81

#define ARM_CPU_PART_CORTEX_X4		0xD82

#define ARM_CPU_PART_NEOVERSE_V3	0xD84

#define ARM_CPU_PART_CORTEX_X925	0xD85

#define ARM_CPU_PART_CORTEX_A725	0xD87



#define APM_CPU_PART_XGENE		0x000

#define APM_CPU_VAR_POTENZA		0x00
@@ -162,9 +167,14 @@ 
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)

#define MIDR_CORTEX_X1C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)

#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)

#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)

#define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)

#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)

#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)

#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)

#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

tools/arch/powerpc/include/uapi/asm/kvm.h

+3 −0
Original line number Diff line number Diff line
@@ -645,6 +645,9 @@ struct kvm_ppc_cpu_char { 
#define KVM_REG_PPC_SIER3	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3)

#define KVM_REG_PPC_DAWR1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4)

#define KVM_REG_PPC_DAWRX1	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5)

#define KVM_REG_PPC_DEXCR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6)

#define KVM_REG_PPC_HASHKEYR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc7)

#define KVM_REG_PPC_HASHPKEYR	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc8)



/* Transactional Memory checkpointed state:

 * This is all GPRs, all VSX regs and a subset of SPRs

tools/arch/x86/include/asm/cpufeatures.h

+403 −400

File changed.

Preview size limit exceeded, changes collapsed.

tools/arch/x86/include/asm/msr-index.h

+11 −0
Original line number Diff line number Diff line
@@ -566,6 +566,12 @@ 
#define MSR_RELOAD_PMC0			0x000014c1

#define MSR_RELOAD_FIXED_CTR0		0x00001309



/* V6 PMON MSR range */

#define MSR_IA32_PMC_V6_GP0_CTR		0x1900

#define MSR_IA32_PMC_V6_GP0_CFG_A	0x1901

#define MSR_IA32_PMC_V6_FX0_CTR		0x1980

#define MSR_IA32_PMC_V6_STEP		4



/* KeyID partitioning between MKTME and TDX */

#define MSR_IA32_MKTME_KEYID_PARTITIONING	0x00000087
@@ -660,6 +666,8 @@ 
#define MSR_AMD64_RMP_BASE		0xc0010132

#define MSR_AMD64_RMP_END		0xc0010133



#define MSR_SVSM_CAA			0xc001f000



/* AMD Collaborative Processor Performance Control MSRs */

#define MSR_AMD_CPPC_CAP1		0xc00102b0

#define MSR_AMD_CPPC_ENABLE		0xc00102b1
@@ -781,6 +789,8 @@ 
#define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

#define MSR_K7_HWCR_CPB_DIS_BIT		25

#define MSR_K7_HWCR_CPB_DIS		BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT)



/* K6 MSRs */

#define MSR_K6_WHCR			0xc0000082
@@ -1164,6 +1174,7 @@ 
#define MSR_IA32_QM_CTR			0xc8e

#define MSR_IA32_PQR_ASSOC		0xc8f

#define MSR_IA32_L3_CBM_BASE		0xc90

#define MSR_RMID_SNC_CONFIG		0xca0

#define MSR_IA32_L2_CBM_BASE		0xd10

#define MSR_IA32_MBA_THRTL_BASE		0xd50

tools/arch/x86/include/uapi/asm/kvm.h

+49 −0
Original line number Diff line number Diff line
@@ -106,6 +106,7 @@ struct kvm_ioapic_state { 


#define KVM_RUN_X86_SMM		 (1 << 0)

#define KVM_RUN_X86_BUS_LOCK     (1 << 1)

#define KVM_RUN_X86_GUEST_MODE   (1 << 2)



/* for KVM_GET_REGS and KVM_SET_REGS */

struct kvm_regs {
@@ -697,6 +698,11 @@ enum sev_cmd_id { 
	/* Second time is the charm; improved versions of the above ioctls.  */

	KVM_SEV_INIT2,



	/* SNP-specific commands */

	KVM_SEV_SNP_LAUNCH_START = 100,

	KVM_SEV_SNP_LAUNCH_UPDATE,

	KVM_SEV_SNP_LAUNCH_FINISH,



	KVM_SEV_NR_MAX,

};
@@ -824,6 +830,48 @@ struct kvm_sev_receive_update_data { 
	__u32 pad2;

};



struct kvm_sev_snp_launch_start {

	__u64 policy;

	__u8 gosvw[16];

	__u16 flags;

	__u8 pad0[6];

	__u64 pad1[4];

};



/* Kept in sync with firmware values for simplicity. */

#define KVM_SEV_SNP_PAGE_TYPE_NORMAL		0x1

#define KVM_SEV_SNP_PAGE_TYPE_ZERO		0x3

#define KVM_SEV_SNP_PAGE_TYPE_UNMEASURED	0x4

#define KVM_SEV_SNP_PAGE_TYPE_SECRETS		0x5

#define KVM_SEV_SNP_PAGE_TYPE_CPUID		0x6



struct kvm_sev_snp_launch_update {

	__u64 gfn_start;

	__u64 uaddr;

	__u64 len;

	__u8 type;

	__u8 pad0;

	__u16 flags;

	__u32 pad1;

	__u64 pad2[4];

};



#define KVM_SEV_SNP_ID_BLOCK_SIZE	96

#define KVM_SEV_SNP_ID_AUTH_SIZE	4096

#define KVM_SEV_SNP_FINISH_DATA_SIZE	32



struct kvm_sev_snp_launch_finish {

	__u64 id_block_uaddr;

	__u64 id_auth_uaddr;

	__u8 id_block_en;

	__u8 auth_key_en;

	__u8 vcek_disabled;

	__u8 host_data[KVM_SEV_SNP_FINISH_DATA_SIZE];

	__u8 pad0[3];

	__u16 flags;

	__u64 pad1[4];

};



#define KVM_X2APIC_API_USE_32BIT_IDS            (1ULL << 0)

#define KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK  (1ULL << 1)
@@ -874,5 +922,6 @@ struct kvm_hyperv_eventfd { 
#define KVM_X86_SW_PROTECTED_VM	1

#define KVM_X86_SEV_VM		2

#define KVM_X86_SEV_ES_VM	3

#define KVM_X86_SNP_VM		4



#endif /* _ASM_X86_KVM_H */