Commit d7b4832c authored by Vinay Belgaumkar's avatar Vinay Belgaumkar Committed by John Harrison
Browse files

drm/i915: Read a shadowed mmio register for ggtt flush 



We read RENDER_HEAD as a part of the flush. If GT is in
deeper sleep states, this could lead to read errors since we are
not using a forcewake. Safer to read a shadowed register instead.

Cc: John Harrison <john.c.harrison@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231109192148.475156-1-vinay.belgaumkar@intel.com
parent 96885303

drivers/gpu/drm/i915/gt/intel_gt.c

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ void intel_gt_flush_ggtt_writes(struct intel_gt *gt) 


		spin_lock_irqsave(&uncore->lock, flags);

		intel_uncore_posting_read_fw(uncore,

					     RING_HEAD(RENDER_RING_BASE));

					     RING_TAIL(RENDER_RING_BASE));

		spin_unlock_irqrestore(&uncore->lock, flags);

	}

}