Commit d7edcc7c authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull more SCSI updates from James Bottomley:
 "This is mostly fixes and cleanups and code reworks that trickled in
  across the merge window and the weeks leading up. The only substantive
  update is the Mediatek ufs driver which accounts for the bulk of the
  additions"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (37 commits)
  scsi: libsas: Use a bool for sas_deform_port() second argument
  scsi: libsas: Move declarations of internal functions to sas_internal.h
  scsi: libsas: Make sas_get_ata_info() static
  scsi: libsas: Simplify sas_ata_wait_eh()
  scsi: libsas: Refactor dev_is_sata()
  scsi: sd: Make sd shutdown issue START STOP UNIT appropriately
  scsi: arm64: dts: mediatek: mt8195: Add UFSHCI node
  scsi: dt-bindings: mediatek,ufs: add MT8195 compatible and update clock nodes
  scsi: dt-bindings: mediatek,ufs: Add ufs-disable-mcq flag for UFS host
  scsi: ufs: ufs-mediatek: Add UFS host support for MT8195 SoC
  scsi: ufs: ufs-pci: Remove control of UIC Completion interrupt for Intel MTL
  scsi: ufs: core: Do not write interrupt enable register unnecessarily
  scsi: ufs: core: Set and clear UIC Completion interrupt as needed
  scsi: ufs: core: Remove duplicated code in ufshcd_send_bsg_uic_cmd()
  scsi: ufs: core: Move ufshcd_enable_intr() and ufshcd_disable_intr()
  scsi: ufs: ufs-pci: Remove UFS PCI driver's ->late_init() call back
  scsi: ufs: ufs-pci: Fix default runtime and system PM levels
  scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers
  scsi: ufs: host: mediatek: Support FDE (AES) clock scaling
  scsi: ufs: host: mediatek: Support clock scaling with Vcore binding
  ...
parents 47905800 7038db70
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+40 −6
Original line number Diff line number Diff line
@@ -9,21 +9,20 @@ title: Mediatek Universal Flash Storage (UFS) Controller
maintainers:
  - Stanley Chu <stanley.chu@mediatek.com>

allOf:
  - $ref: ufs-common.yaml

properties:
  compatible:
    enum:
      - mediatek,mt8183-ufshci
      - mediatek,mt8192-ufshci
      - mediatek,mt8195-ufshci

  clocks:
    maxItems: 1
    minItems: 1
    maxItems: 8

  clock-names:
    items:
      - const: ufs
    minItems: 1
    maxItems: 8

  phys:
    maxItems: 1
@@ -33,6 +32,10 @@ properties:

  vcc-supply: true

  mediatek,ufs-disable-mcq:
    $ref: /schemas/types.yaml#/definitions/flag
    description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.

required:
  - compatible
  - clocks
@@ -43,6 +46,37 @@ required:

unevaluatedProperties: false

allOf:
  - $ref: ufs-common.yaml

  - if:
      properties:
        compatible:
          contains:
            enum:
              - mediatek,mt8195-ufshci
    then:
      properties:
        clocks:
          minItems: 8
        clock-names:
          items:
            - const: ufs
            - const: ufs_aes
            - const: ufs_tick
            - const: unipro_sysclk
            - const: unipro_tick
            - const: unipro_mp_bclk
            - const: ufs_tx_symbol
            - const: ufs_mem_sub
    else:
      properties:
        clocks:
          maxItems: 1
        clock-names:
          items:
            - const: ufs

examples:
  - |
    #include <dt-bindings/clock/mt8183-clk.h>
+1 −1
Original line number Diff line number Diff line
@@ -11100,7 +11100,7 @@ F: Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
F:	drivers/infiniband/hw/hns/
HISILICON SAS Controller
M:	Yihang Li <liyihang9@huawei.com>
M:	Yihang Li <liyihang9@h-partners.com>
S:	Supported
W:	http://www.hisilicon.com
F:	Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
+25 −0
Original line number Diff line number Diff line
@@ -1430,6 +1430,31 @@ mmc2: mmc@11250000 {
			status = "disabled";
		};

		ufshci: ufshci@11270000 {
			compatible = "mediatek,mt8195-ufshci";
			reg = <0 0x11270000 0 0x2300>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
			phys = <&ufsphy>;
			clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>,
				 <&infracfg_ao CLK_INFRA_AO_AES>,
				 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
				 <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>,
				 <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>,
				 <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>,
				 <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>,
				 <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
			clock-names = "ufs", "ufs_aes", "ufs_tick",
					"unipro_sysclk", "unipro_tick",
					"unipro_mp_bclk", "ufs_tx_symbol",
					"ufs_mem_sub";
			freq-table-hz = <0 0>, <0 0>, <0 0>,
					<0 0>, <0 0>, <0 0>,
					<0 0>, <0 0>;

			mediatek,ufs-disable-mcq;
			status = "disabled";
		};

		lvts_mcu: thermal-sensor@11278000 {
			compatible = "mediatek,mt8195-lvts-mcu";
			reg = <0 0x11278000 0 0x1000>;
+1 −2
Original line number Diff line number Diff line
@@ -481,8 +481,7 @@ void aac_define_int_mode(struct aac_dev *dev)
	    pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX)) {
		min_msix = 2;
		i = pci_alloc_irq_vectors(dev->pdev,
					  min_msix, msi_count,
					  PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
					  min_msix, msi_count, PCI_IRQ_MSIX);
		if (i > 0) {
			dev->msi_enabled = 1;
			msi_count = i;
+2 −8
Original line number Diff line number Diff line
@@ -252,7 +252,7 @@ static int sas_get_ata_command_set(struct domain_device *dev)
	return ata_dev_classify(&tf);
}

int sas_get_ata_info(struct domain_device *dev, struct ex_phy *phy)
static int sas_get_ata_info(struct domain_device *dev, struct ex_phy *phy)
{
	if (phy->attached_tproto & SAS_PROTOCOL_STP)
		dev->tproto = phy->attached_tproto;
@@ -927,13 +927,7 @@ EXPORT_SYMBOL_GPL(sas_ata_schedule_reset);

void sas_ata_wait_eh(struct domain_device *dev)
{
	struct ata_port *ap;

	if (!dev_is_sata(dev))
		return;

	ap = dev->sata_dev.ap;
	ata_port_wait_eh(ap);
	ata_port_wait_eh(dev->sata_dev.ap);
}

void sas_ata_device_link_abort(struct domain_device *device, bool force_reset)
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