Commit d7fe0d42 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'tegra-for-5.14-arm64-dt' of... 

Merge tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v5.14-rc1

Contains changes to consolidate audio card names, adds audio support on
Jetson Xavier NX and enables SMMU on Tegra194.

* tag 'tegra-for-5.14-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Enable SMMU support on Tegra194
  arm64: tegra: Hook up memory controller to SMMU on Tegra186
  arm64: tegra: Use correct compatible string for Tegra186 SMMU
  arm64: tegra: Audio graph sound card for Jetson Xavier NX
  arm64: tegra: Consolidate audio card names
  arm64: tegra: Add PMU node for Tegra194

Link: https://lore.kernel.org/r/20210611164437.3568059-6-thierry.reding@gmail.com


Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 8fb202c7 c7289b1c

arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts

+2 −2
Original line number Diff line number Diff line
@@ -817,7 +817,7 @@ mmc@3400000 { 
	};



	hda@3510000 {

		nvidia,model = "jetson-tx2-hda";

		nvidia,model = "NVIDIA Jetson TX2 HDA";

		status = "okay";

	};
@@ -1109,6 +1109,6 @@ sound { 
		       <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,

		       <&dmic3_port>, <&dspk1_port>, <&dspk2_port>;



		label = "jetson-tx2-ape";

		label = "NVIDIA Jetson TX2 APE";

	};

};

arch/arm64/boot/dts/nvidia/tegra186.dtsi

+3 −1
Original line number Diff line number Diff line
@@ -1082,7 +1082,7 @@ pci@3,0 { 
	};



	smmu: iommu@12000000 {

		compatible = "arm,mmu-500";

		compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";

		reg = <0 0x12000000 0 0x800000>;

		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -1152,6 +1152,8 @@ smmu: iommu@12000000 { 
		stream-match-mask = <0x7f80>;

		#global-interrupts = <1>;

		#iommu-cells = <1>;



		nvidia,memory-controller = <&mc>;

	};



	host1x@13e00000 {

arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts

+2 −2
Original line number Diff line number Diff line
@@ -554,7 +554,7 @@ mmc@3400000 { 
		};



		hda@3510000 {

			nvidia,model = "jetson-xavier-hda";

			nvidia,model = "NVIDIA Jetson AGX Xavier HDA";

			status = "okay";

		};
@@ -831,7 +831,7 @@ sound { 
		       <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,

		       <&dmic3_port>;



		label = "jetson-xavier-ape";

		label = "NVIDIA Jetson AGX Xavier APE";



		widgets =

			"Microphone",	"CVB-RT MIC Jack",

arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi

+594 −1
Original line number Diff line number Diff line
@@ -15,6 +15,577 @@ dma-controller@2930000 { 
			interrupt-controller@2a40000 {

				status = "okay";

			};



			ahub@2900800 {

				status = "okay";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0x0>;



						xbar_admaif0_ep: endpoint {

							remote-endpoint = <&admaif0_ep>;

						};

					};



					port@1 {

						reg = <0x1>;



						xbar_admaif1_ep: endpoint {

							remote-endpoint = <&admaif1_ep>;

						};

					};



					port@2 {

						reg = <0x2>;



						xbar_admaif2_ep: endpoint {

							remote-endpoint = <&admaif2_ep>;

						};

					};



					port@3 {

						reg = <0x3>;



						xbar_admaif3_ep: endpoint {

							remote-endpoint = <&admaif3_ep>;

						};

					};



					port@4 {

						reg = <0x4>;



						xbar_admaif4_ep: endpoint {

							remote-endpoint = <&admaif4_ep>;

						};

					};



					port@5 {

						reg = <0x5>;



						xbar_admaif5_ep: endpoint {

							remote-endpoint = <&admaif5_ep>;

						};

					};



					port@6 {

						reg = <0x6>;



						xbar_admaif6_ep: endpoint {

							remote-endpoint = <&admaif6_ep>;

						};

					};



					port@7 {

						reg = <0x7>;



						xbar_admaif7_ep: endpoint {

							remote-endpoint = <&admaif7_ep>;

						};

					};



					port@8 {

						reg = <0x8>;



						xbar_admaif8_ep: endpoint {

							remote-endpoint = <&admaif8_ep>;

						};

					};



					port@9 {

						reg = <0x9>;



						xbar_admaif9_ep: endpoint {

							remote-endpoint = <&admaif9_ep>;

						};

					};



					port@a {

						reg = <0xa>;



						xbar_admaif10_ep: endpoint {

							remote-endpoint = <&admaif10_ep>;

						};

					};



					port@b {

						reg = <0xb>;



						xbar_admaif11_ep: endpoint {

							remote-endpoint = <&admaif11_ep>;

						};

					};



					port@c {

						reg = <0xc>;



						xbar_admaif12_ep: endpoint {

							remote-endpoint = <&admaif12_ep>;

						};

					};



					port@d {

						reg = <0xd>;



						xbar_admaif13_ep: endpoint {

							remote-endpoint = <&admaif13_ep>;

						};

					};



					port@e {

						reg = <0xe>;



						xbar_admaif14_ep: endpoint {

							remote-endpoint = <&admaif14_ep>;

						};

					};



					port@f {

						reg = <0xf>;



						xbar_admaif15_ep: endpoint {

							remote-endpoint = <&admaif15_ep>;

						};

					};



					port@10 {

						reg = <0x10>;



						xbar_admaif16_ep: endpoint {

							remote-endpoint = <&admaif16_ep>;

						};

					};



					port@11 {

						reg = <0x11>;



						xbar_admaif17_ep: endpoint {

							remote-endpoint = <&admaif17_ep>;

						};

					};



					port@12 {

						reg = <0x12>;



						xbar_admaif18_ep: endpoint {

							remote-endpoint = <&admaif18_ep>;

						};

					};



					port@13 {

						reg = <0x13>;



						xbar_admaif19_ep: endpoint {

							remote-endpoint = <&admaif19_ep>;

						};

					};



					xbar_i2s3_port: port@16 {

						reg = <0x16>;



						xbar_i2s3_ep: endpoint {

							remote-endpoint = <&i2s3_cif_ep>;

						};

					};



					xbar_i2s5_port: port@18 {

						reg = <0x18>;



						xbar_i2s5_ep: endpoint {

							remote-endpoint = <&i2s5_cif_ep>;

						};

					};



					xbar_dmic1_port: port@1a {

						reg = <0x1a>;



						xbar_dmic1_ep: endpoint {

							remote-endpoint = <&dmic1_cif_ep>;

						};

					};



					xbar_dmic2_port: port@1b {

						reg = <0x1b>;



						xbar_dmic2_ep: endpoint {

							remote-endpoint = <&dmic2_cif_ep>;

						};

					};



					xbar_dmic4_port: port@1d {

						reg = <0x1d>;



						xbar_dmic4_ep: endpoint {

							remote-endpoint = <&dmic4_cif_ep>;

						};

					};



					xbar_dspk1_port: port@1e {

						reg = <0x1e>;



						xbar_dspk1_ep: endpoint {

							remote-endpoint = <&dspk1_cif_ep>;

						};

					};



					xbar_dspk2_port: port@1f {

						reg = <0x1f>;



						xbar_dspk2_ep: endpoint {

							remote-endpoint = <&dspk2_cif_ep>;

						};

					};

				};



				admaif@290f000 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						admaif0_port: port@0 {

							reg = <0x0>;



							admaif0_ep: endpoint {

								remote-endpoint = <&xbar_admaif0_ep>;

							};

						};



						admaif1_port: port@1 {

							reg = <0x1>;



							admaif1_ep: endpoint {

								remote-endpoint = <&xbar_admaif1_ep>;

							};

						};



						admaif2_port: port@2 {

							reg = <0x2>;



							admaif2_ep: endpoint {

								remote-endpoint = <&xbar_admaif2_ep>;

							};

						};



						admaif3_port: port@3 {

							reg = <0x3>;



							admaif3_ep: endpoint {

								remote-endpoint = <&xbar_admaif3_ep>;

							};

						};



						admaif4_port: port@4 {

							reg = <0x4>;



							admaif4_ep: endpoint {

								remote-endpoint = <&xbar_admaif4_ep>;

							};

						};



						admaif5_port: port@5 {

							reg = <0x5>;



							admaif5_ep: endpoint {

								remote-endpoint = <&xbar_admaif5_ep>;

							};

						};



						admaif6_port: port@6 {

							reg = <0x6>;



							admaif6_ep: endpoint {

								remote-endpoint = <&xbar_admaif6_ep>;

							};

						};



						admaif7_port: port@7 {

							reg = <0x7>;



							admaif7_ep: endpoint {

								remote-endpoint = <&xbar_admaif7_ep>;

							};

						};



						admaif8_port: port@8 {

							reg = <0x8>;



							admaif8_ep: endpoint {

								remote-endpoint = <&xbar_admaif8_ep>;

							};

						};



						admaif9_port: port@9 {

							reg = <0x9>;



							admaif9_ep: endpoint {

								remote-endpoint = <&xbar_admaif9_ep>;

							};

						};



						admaif10_port: port@a {

							reg = <0xa>;



							admaif10_ep: endpoint {

								remote-endpoint = <&xbar_admaif10_ep>;

							};

						};



						admaif11_port: port@b {

							reg = <0xb>;



							admaif11_ep: endpoint {

								remote-endpoint = <&xbar_admaif11_ep>;

							};

						};



						admaif12_port: port@c {

							reg = <0xc>;



							admaif12_ep: endpoint {

								remote-endpoint = <&xbar_admaif12_ep>;

							};

						};



						admaif13_port: port@d {

							reg = <0xd>;



							admaif13_ep: endpoint {

								remote-endpoint = <&xbar_admaif13_ep>;

							};

						};



						admaif14_port: port@e {

							reg = <0xe>;



							admaif14_ep: endpoint {

								remote-endpoint = <&xbar_admaif14_ep>;

							};

						};



						admaif15_port: port@f {

							reg = <0xf>;



							admaif15_ep: endpoint {

								remote-endpoint = <&xbar_admaif15_ep>;

							};

						};



						admaif16_port: port@10 {

							reg = <0x10>;



							admaif16_ep: endpoint {

								remote-endpoint = <&xbar_admaif16_ep>;

							};

						};



						admaif17_port: port@11 {

							reg = <0x11>;



							admaif17_ep: endpoint {

								remote-endpoint = <&xbar_admaif17_ep>;

							};

						};



						admaif18_port: port@12 {

							reg = <0x12>;



							admaif18_ep: endpoint {

								remote-endpoint = <&xbar_admaif18_ep>;

							};

						};



						admaif19_port: port@13 {

							reg = <0x13>;



							admaif19_ep: endpoint {

								remote-endpoint = <&xbar_admaif19_ep>;

							};

						};

					};

				};



				i2s@2901200 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							i2s3_cif_ep: endpoint {

								remote-endpoint = <&xbar_i2s3_ep>;

							};

						};



						i2s3_port: port@1 {

							reg = <1>;



							i2s3_dap_ep: endpoint {

								dai-format = "i2s";

								/* Place holder for external Codec */

							};

						};

					};

				};



				i2s@2901400 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							i2s5_cif_ep: endpoint {

								remote-endpoint = <&xbar_i2s5_ep>;

							};

						};



						i2s5_port: port@1 {

							reg = <1>;



							i2s5_dap_ep: endpoint@0 {

								dai-format = "i2s";

								/* Place holder for external Codec */

							};

						};

					};

				};



				dmic@2904000 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							dmic1_cif_ep: endpoint {

								remote-endpoint = <&xbar_dmic1_ep>;

							};

						};



						dmic1_port: port@1 {

							reg = <1>;



							dmic1_dap_ep: endpoint {

								/* Place holder for external Codec */

							};

						};

					};

				};



				dmic@2904100 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							dmic2_cif_ep: endpoint {

								remote-endpoint = <&xbar_dmic2_ep>;

							};

						};



						dmic2_port: port@1 {

							reg = <1>;



							dmic2_dap_ep: endpoint {

								/* Place holder for external Codec */

							};

						};

					};

				};



				dmic@2904300 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							dmic4_cif_ep: endpoint {

								remote-endpoint = <&xbar_dmic4_ep>;

							};

						};



						dmic4_port: port@1 {

							reg = <1>;



							dmic4_dap_ep: endpoint {

								/* Place holder for external Codec */

							};

						};

					};

				};



				dspk@2905000 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							dspk1_cif_ep: endpoint {

								remote-endpoint = <&xbar_dspk1_ep>;

							};

						};



						dspk1_port: port@1 {

							reg = <1>;



							dspk1_dap_ep: endpoint {

								/* Place holder for external Codec */

							};

						};

					};

				};



				dspk@2905100 {

					status = "okay";



					ports {

						#address-cells = <1>;

						#size-cells = <0>;



						port@0 {

							reg = <0>;



							dspk2_cif_ep: endpoint {

								remote-endpoint = <&xbar_dspk2_ep>;

							};

						};



						dspk2_port: port@1 {

							reg = <1>;



							dspk2_dap_ep: endpoint {

								/* Place holder for external Codec */

							};

						};

					};

				};

			};

		};



		ddc: i2c@3190000 {
@@ -36,7 +607,7 @@ eeprom@57 { 
		};



		hda@3510000 {

			nvidia,model = "jetson-xavier-nx-hda";

			nvidia,model = "NVIDIA Jetson Xavier NX HDA";

			status = "okay";

		};
@@ -265,6 +836,28 @@ vdd_hdmi: regulator@104 { 
		regulator-boot-on;

	};



	sound {

		compatible = "nvidia,tegra186-audio-graph-card";

		status = "okay";



		dais = /* ADMAIF (FE) Ports */

		       <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,

		       <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,

		       <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,

		       <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,

		       <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,

		       /* XBAR Ports */

		       <&xbar_i2s3_port>, <&xbar_i2s5_port>,

		       <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,

		       <&xbar_dspk1_port>, <&xbar_dspk2_port>,

		       /* BE I/O Ports */

		       <&i2s3_port>, <&i2s5_port>,

		       <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,

		       <&dspk1_port>, <&dspk2_port>;



		label = "NVIDIA Jetson Xavier NX APE";

	};



	thermal-zones {

		cpu {

			polling-delay = <0>;

arch/arm64/boot/dts/nvidia/tegra194.dtsi

+100 −0
Original line number Diff line number Diff line
@@ -62,6 +62,7 @@ ethernet@2490000 { 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_EQOS>;

			status = "disabled";



			snps,write-requests = <1>;
@@ -733,6 +734,7 @@ sdmmc1: mmc@3400000 { 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC1>;

			nvidia,pad-autocal-pull-up-offset-3v3-timeout =

									<0x07>;

			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@ sdmmc3: mmc@3440000 { 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC3>;

			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;

			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;

			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@ sdmmc4: mmc@3460000 { 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_SDMMC4>;

			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;

			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@ hda@3510000 { 
			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,

					<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;

			interconnect-names = "dma-mem", "write";

			iommus = <&smmu TEGRA194_SID_HDA>;

			status = "disabled";

		};
@@ -1300,6 +1305,84 @@ pmc: pmc@c360000 { 
			interrupt-controller;

		};



		smmu: iommu@12000000 {

			compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";

			reg = <0x12000000 0x800000>,

			      <0x11000000 0x800000>;

			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;

			stream-match-mask = <0x7f80>;

			#global-interrupts = <2>;

			#iommu-cells = <1>;



			nvidia,memory-controller = <&mc>;

			status = "okay";

		};



		host1x@13e00000 {

			compatible = "nvidia,tegra194-host1x";

			reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@ host1x@13e00000 { 
			ranges = <0x15000000 0x15000000 0x01000000>;

			interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;

			interconnect-names = "dma-mem";

			iommus = <&smmu TEGRA194_SID_HOST1X>;



			display-hub@15200000 {

				compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@ vic@15340000 { 
				interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,

						<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;

				interconnect-names = "dma-mem", "write";

				iommus = <&smmu TEGRA194_SID_VIC>;

			};



			dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@ bpmp: bpmp { 
				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,

				<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;

		interconnect-names = "read", "write", "dma-mem", "dma-write";

		iommus = <&smmu TEGRA194_SID_BPMP>;



		bpmp_i2c: i2c {

			compatible = "nvidia,tegra186-bpmp-i2c";
@@ -2345,6 +2431,20 @@ l3c: l3-cache { 
		};

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1

				      &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;

	};



	psci {

		compatible = "arm,psci-1.0";

		status = "okay";