Commit d8066764 authored by Yannick Fertre's avatar Yannick Fertre Committed by Raphael Gallais-Pou
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drm/stm: ltdc: support new hardware version for STM32MP25 SoC 



STM32MP25 SoC features a new version of the LTDC IP.  Add its compatible
to the list of device to probe and implement its quirks.

This hardware supports a pad frequency of 150MHz and a peripheral bus
clock.

Signed-off-by: default avatarYannick Fertre <yannick.fertre@foss.st.com>
Acked-by: default avatarYannick Fertre <yannick.fertre@foss.st.com>
Acked-by: default avatarPhilippe Cornu <philippe.cornu@foss.st.com>
Link: https://lore.kernel.org/r/20250822-drm-misc-next-v5-7-9c825e28f733@foss.st.com


Signed-off-by: default avatarRaphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
parent 1b9482f8

drivers/gpu/drm/stm/drv.c

+11 −1
Original line number Diff line number Diff line
@@ -236,8 +236,18 @@ static void stm_drm_platform_shutdown(struct platform_device *pdev) 
	drm_atomic_helper_shutdown(platform_get_drvdata(pdev));

}



static struct ltdc_plat_data stm_drm_plat_data = {

	.pad_max_freq_hz = 90000000,

};



static struct ltdc_plat_data stm_drm_plat_data_mp25 = {

	.pad_max_freq_hz = 150000000,

};



static const struct of_device_id drv_dt_ids[] = {

	{ .compatible = "st,stm32-ltdc"},

	{ .compatible = "st,stm32-ltdc", .data = &stm_drm_plat_data, },

	{ .compatible = "st,stm32mp251-ltdc", .data = &stm_drm_plat_data_mp25, },

	{ .compatible = "st,stm32mp255-ltdc", .data = &stm_drm_plat_data_mp25, },

	{ /* end node */ },

};

MODULE_DEVICE_TABLE(of, drv_dt_ids);

drivers/gpu/drm/stm/ltdc.c

+35 −3
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ 
#include <linux/interrupt.h>

#include <linux/media-bus-format.h>

#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_graph.h>

#include <linux/pinctrl/consumer.h>

#include <linux/platform_device.h>
@@ -51,6 +52,7 @@ 
#define HWVER_10300 0x010300

#define HWVER_20101 0x020101

#define HWVER_40100 0x040100

#define HWVER_40101 0x040101



/*

 * The address of some registers depends on the HW version: such registers have
@@ -1780,6 +1782,7 @@ static int ltdc_get_caps(struct drm_device *ddev) 
{

	struct ltdc_device *ldev = ddev->dev_private;

	u32 bus_width_log2, lcr, gc2r;

	const struct ltdc_plat_data *pdata = of_device_get_match_data(ddev->dev);



	/*

	 * at least 1 layer must be managed & the number of layers
@@ -1795,6 +1798,8 @@ static int ltdc_get_caps(struct drm_device *ddev) 
	ldev->caps.bus_width = 8 << bus_width_log2;

	regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);



	ldev->caps.pad_max_freq_hz = pdata->pad_max_freq_hz;



	switch (ldev->caps.hw_version) {

	case HWVER_10200:

	case HWVER_10300:
@@ -1812,7 +1817,6 @@ static int ltdc_get_caps(struct drm_device *ddev) 
		 * does not work on 2nd layer.

		 */

		ldev->caps.non_alpha_only_l1 = true;

		ldev->caps.pad_max_freq_hz = 90000000;

		if (ldev->caps.hw_version == HWVER_10200)

			ldev->caps.pad_max_freq_hz = 65000000;

		ldev->caps.nb_irq = 2;
@@ -1843,6 +1847,7 @@ static int ltdc_get_caps(struct drm_device *ddev) 
		ldev->caps.fifo_threshold = false;

		break;

	case HWVER_40100:

	case HWVER_40101:

		ldev->caps.layer_ofs = LAY_OFS_1;

		ldev->caps.layer_regs = ltdc_layer_regs_a2;

		ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
@@ -1850,7 +1855,6 @@ static int ltdc_get_caps(struct drm_device *ddev) 
		ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);

		ldev->caps.pix_fmt_flex = true;

		ldev->caps.non_alpha_only_l1 = false;

		ldev->caps.pad_max_freq_hz = 90000000;

		ldev->caps.nb_irq = 2;

		ldev->caps.ycbcr_input = true;

		ldev->caps.ycbcr_output = true;
@@ -1873,6 +1877,8 @@ void ltdc_suspend(struct drm_device *ddev) 


	drm_dbg_driver(ddev, "\n");

	clk_disable_unprepare(ldev->pixel_clk);

	if (ldev->bus_clk)

		clk_disable_unprepare(ldev->bus_clk);

}



int ltdc_resume(struct drm_device *ddev)
@@ -1888,7 +1894,13 @@ int ltdc_resume(struct drm_device *ddev) 
		return ret;

	}



	return 0;

	if (ldev->bus_clk) {

		ret = clk_prepare_enable(ldev->bus_clk);

		if (ret)

			drm_err(ddev, "failed to enable bus clock (%d)\n", ret);

	}



	return ret;

}



int ltdc_load(struct drm_device *ddev)
@@ -1923,6 +1935,20 @@ int ltdc_load(struct drm_device *ddev) 
		return -ENODEV;

	}



	if (of_device_is_compatible(np, "st,stm32mp251-ltdc") ||

	    of_device_is_compatible(np, "st,stm32mp255-ltdc")) {

		ldev->bus_clk = devm_clk_get(dev, "bus");

		if (IS_ERR(ldev->bus_clk))

			return dev_err_probe(dev, PTR_ERR(ldev->bus_clk),

					     "Unable to get bus clock\n");



		ret = clk_prepare_enable(ldev->bus_clk);

		if (ret) {

			drm_err(ddev, "Unable to prepare bus clock\n");

			return ret;

		}

	}



	/* Get endpoints if any */

	for (i = 0; i < nb_endpoints; i++) {

		ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
@@ -2035,6 +2061,9 @@ int ltdc_load(struct drm_device *ddev) 


	clk_disable_unprepare(ldev->pixel_clk);



	if (ldev->bus_clk)

		clk_disable_unprepare(ldev->bus_clk);



	pinctrl_pm_select_sleep_state(ddev->dev);



	pm_runtime_enable(ddev->dev);
@@ -2043,6 +2072,9 @@ int ltdc_load(struct drm_device *ddev) 
err:

	clk_disable_unprepare(ldev->pixel_clk);



	if (ldev->bus_clk)

		clk_disable_unprepare(ldev->bus_clk);



	return ret;

}

drivers/gpu/drm/stm/ltdc.h

+5 −0
Original line number Diff line number Diff line
@@ -40,10 +40,15 @@ struct fps_info { 
	ktime_t last_timestamp;

};



struct ltdc_plat_data {

	int pad_max_freq_hz;	/* max frequency supported by pad */

};



struct ltdc_device {

	void __iomem *regs;

	struct regmap *regmap;

	struct clk *pixel_clk;	/* lcd pixel clock */

	struct clk *bus_clk;	/* bus clock */

	struct mutex err_lock;	/* protecting error_status */

	struct ltdc_caps caps;

	u32 irq_status;