Commit d806f474 authored by Prathamesh Shete's avatar Prathamesh Shete Committed by Bartosz Golaszewski
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gpio: tegra186: Fix tegra186_gpio_is_accessible() check 



The controller has several register bits describing access control
information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it
means we have full read/write access to all the registers for given GPIO
pin. When SCR_SEC[R|W]EN is set, it means we need to further check the
accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all
the registers for given GPIO pin.

This check was previously declaring that a GPIO pin was accessible
only if either of the following conditions were met:

  - SCR_SEC_REN + SCR_SEC_WEN both set

    or

  - SCR_SEC_REN + SCR_SEC_WEN both set and
    SCR_SEC_G1R + SCR_SEC_G1W both set

Update the check to properly handle cases where only one of
SCR_SEC_REN or SCR_SEC_WEN is set.

Fixes: b2b56a16 ("gpio: tegra186: Check GPIO pin permission before access.")
Signed-off-by: default avatarPrathamesh Shete <pshete@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20240424095514.24397-1-pshete@nvidia.com


Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent ed30a4a5

drivers/gpio/gpio-tegra186.c

+11 −9
Original line number Diff line number Diff line
@@ -36,12 +36,6 @@ 
#define  TEGRA186_GPIO_SCR_SEC_REN		BIT(27)

#define  TEGRA186_GPIO_SCR_SEC_G1W		BIT(9)

#define  TEGRA186_GPIO_SCR_SEC_G1R		BIT(1)

#define  TEGRA186_GPIO_FULL_ACCESS		(TEGRA186_GPIO_SCR_SEC_WEN | \

						 TEGRA186_GPIO_SCR_SEC_REN | \

						 TEGRA186_GPIO_SCR_SEC_G1R | \

						 TEGRA186_GPIO_SCR_SEC_G1W)

#define  TEGRA186_GPIO_SCR_SEC_ENABLE		(TEGRA186_GPIO_SCR_SEC_WEN | \

						 TEGRA186_GPIO_SCR_SEC_REN)



/* control registers */

#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
@@ -177,10 +171,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned 


	value = __raw_readl(secure + TEGRA186_GPIO_SCR);



	if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0)

		return true;

	/*

	 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the

	 * registers for given GPIO pin.

	 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying

	 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given

	 * GPIO pin.

	 */



	if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS)

	if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||

	     ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&

	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||

	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))

		return true;



	return false;