Commit d81826f8 authored by James Morse's avatar James Morse Committed by Borislav Petkov (AMD)
Browse files

x86/resctrl: Add resctrl_arch_is_evt_configurable() to abstract BMEC



When BMEC is supported the resctrl event can be configured in a number of
ways. This depends on architecture support. rdt_get_mon_l3_config() modifies
the struct mon_evt and calls resctrl_file_fflags_init() to create the files
that allow the configuration.

Splitting this into separate architecture and filesystem parts would require
the struct mon_evt and resctrl_file_fflags_init() to be exposed.

Instead, add resctrl_arch_is_evt_configurable(), and use this from
resctrl_mon_resource_init() to initialise struct mon_evt and call
resctrl_file_fflags_init().

resctrl_arch_is_evt_configurable() calls rdt_cpu_has() so it doesn't obviously
benefit from being inlined. Putting it in core.c will allow rdt_cpu_has() to
eventually become static.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: default avatarShaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Reviewed-by: default avatarTony Luck <tony.luck@intel.com>
Reviewed-by: default avatarFenghua Yu <fenghuay@nvidia.com>
Reviewed-by: default avatarReinette Chatre <reinette.chatre@intel.com>
Reviewed-by: default avatarBabu Moger <babu.moger@amd.com>
Tested-by: Carl Worth <carl@os.amperecomputing.com> # arm64
Tested-by: default avatarShaopeng Tan <tan.shaopeng@jp.fujitsu.com>
Tested-by: default avatarPeter Newman <peternewman@google.com>
Tested-by: Amit Singh Tomar <amitsinght@marvell.com> # arm64
Tested-by: Shanker Donthineni <sdonthineni@nvidia.com> # arm64
Tested-by: default avatarBabu Moger <babu.moger@amd.com>
Link: https://lore.kernel.org/r/20250311183715.16445-20-james.morse@arm.com
parent d012b66a
Loading
Loading
Loading
Loading
+15 −0
Original line number Diff line number Diff line
@@ -830,6 +830,21 @@ bool __init rdt_cpu_has(int flag)
	return ret;
}

__init bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt)
{
	if (!rdt_cpu_has(X86_FEATURE_BMEC))
		return false;

	switch (evt) {
	case QOS_L3_MBM_TOTAL_EVENT_ID:
		return rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL);
	case QOS_L3_MBM_LOCAL_EVENT_ID:
		return rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL);
	default:
		return false;
	}
}

static __init bool get_mem_config(void)
{
	struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_MBA];
+11 −11
Original line number Diff line number Diff line
@@ -1202,6 +1202,17 @@ int __init resctrl_mon_resource_init(void)

	l3_mon_evt_init(r);

	if (resctrl_arch_is_evt_configurable(QOS_L3_MBM_TOTAL_EVENT_ID)) {
		mbm_total_event.configurable = true;
		resctrl_file_fflags_init("mbm_total_bytes_config",
					 RFTYPE_MON_INFO | RFTYPE_RES_CACHE);
	}
	if (resctrl_arch_is_evt_configurable(QOS_L3_MBM_LOCAL_EVENT_ID)) {
		mbm_local_event.configurable = true;
		resctrl_file_fflags_init("mbm_local_bytes_config",
					 RFTYPE_MON_INFO | RFTYPE_RES_CACHE);
	}

	return 0;
}

@@ -1245,17 +1256,6 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r)
		/* Detect list of bandwidth sources that can be tracked */
		cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx);
		hw_res->mbm_cfg_mask = ecx & MAX_EVT_CONFIG_BITS;

		if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) {
			mbm_total_event.configurable = true;
			resctrl_file_fflags_init("mbm_total_bytes_config",
						 RFTYPE_MON_INFO | RFTYPE_RES_CACHE);
		}
		if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) {
			mbm_local_event.configurable = true;
			resctrl_file_fflags_init("mbm_local_bytes_config",
						 RFTYPE_MON_INFO | RFTYPE_RES_CACHE);
		}
	}

	r->mon_capable = true;
+2 −0
Original line number Diff line number Diff line
@@ -309,6 +309,8 @@ u32 resctrl_arch_get_num_closid(struct rdt_resource *r);
u32 resctrl_arch_system_num_rmid_idx(void);
int resctrl_arch_update_domains(struct rdt_resource *r, u32 closid);

__init bool resctrl_arch_is_evt_configurable(enum resctrl_event_id evt);

/*
 * Update the ctrl_val and apply this config right now.
 * Must be called on one of the domain's CPUs.