Commit d85cb4ff authored by John Madieu's avatar John Madieu Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a09g047: Add PCIe clocks and reset 



Add necessary clocks and reset entries for the PCIe controller.

Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarJohn Madieu <john.madieu.xa@bp.renesas.com>
Reviewed-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: default avatarClaudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Link: https://patch.msgid.link/20260318085119.44717-2-john.madieu.xa@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent c45d9beb

drivers/clk/renesas/r9a09g047-cpg.c

+5 −0
Original line number Diff line number Diff line
@@ -442,6 +442,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("gbeth_1_aclk_i",		CLK_PLLDTY_DIV8, 12, 3, 6, 3,

						BUS_MSTOP(8, BIT(6))),

	DEF_MOD("pcie_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,

						BUS_MSTOP(1, BIT(15))),

	DEF_MOD("pcie_0_clk_pmu",		CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,

						BUS_MSTOP(1, BIT(15))),

	DEF_MOD("cru_0_aclk",			CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,

						BUS_MSTOP(9, BIT(4))),

	DEF_MOD_NO_PM("cru_0_vclk",		CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -527,6 +531,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

	DEF_RST(11, 0, 5, 1),		/* GBETH_0_ARESETN_I */

	DEF_RST(11, 1, 5, 2),		/* GBETH_1_ARESETN_I */

	DEF_RST(11, 2, 5, 3),		/* PCIE_0_ARESETN */

	DEF_RST(12, 5, 5, 22),		/* CRU_0_PRESETN */

	DEF_RST(12, 6, 5, 23),		/* CRU_0_ARESETN */

	DEF_RST(12, 7, 5, 24),		/* CRU_0_S_RESETN */