Commit d863a2f4 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: freescale: imx8-ss-lsio: Fix #pwm-cells 



i.MX8QM/QXP supports inverted PWM output, thus #pwm-cells needs to be set
to 3.

Fixes: 23fa99b2 ("arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3")
Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 4c6f19ab

arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ lsio_pwm0: pwm@5d000000 { 
			 <&pwm0_lpcg 1>;

		assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <24000000>;

		#pwm-cells = <2>;

		#pwm-cells = <3>;

		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};
@@ -42,7 +42,7 @@ lsio_pwm1: pwm@5d010000 { 
			 <&pwm1_lpcg 1>;

		assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <24000000>;

		#pwm-cells = <2>;

		#pwm-cells = <3>;

		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};
@@ -55,7 +55,7 @@ lsio_pwm2: pwm@5d020000 { 
			 <&pwm2_lpcg 1>;

		assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <24000000>;

		#pwm-cells = <2>;

		#pwm-cells = <3>;

		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};
@@ -68,7 +68,7 @@ lsio_pwm3: pwm@5d030000 { 
			 <&pwm3_lpcg 1>;

		assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;

		assigned-clock-rates = <24000000>;

		#pwm-cells = <2>;

		#pwm-cells = <3>;

		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

		status = "disabled";

	};