Unverified Commit d8b210f8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 

Pull Amlogic clk driver updates from Jerome Brunet:

 - Add support for Amlogic t7 clock controllers
 - Add video clocks on Amlogic s4
 - HDMI PLL post divider fixes on Amlogic gx/g12 SoCs

* tag 'clk-meson-v6.20-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: gxbb: use the existing HHI_HDMI_PLL_CNTL3 macro
  clk: meson: g12a: Limit the HDMI PLL OD to /4
  clk: meson: gxbb: Limit the HDMI PLL OD to /4 on GXL/GXM SoCs
  clk: amlogic: remove potentially unsafe flags from S4 video clocks
  clk: amlogic: add video-related clocks for S4 SoC
  dt-bindings: clock: add video clock indices for Amlogic S4 SoC
  clk: meson: t7: add t7 clock peripherals controller driver
  clk: meson: t7: add support for the T7 SoC PLL clock
  dt-bindings: clock: add Amlogic T7 peripherals clock controller
  dt-bindings: clock: add Amlogic T7 SCMI clock controller
  dt-bindings: clock: add Amlogic T7 PLL clock controller
parents 8f0b4cce 2fe1ef40

Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic T7 Peripherals Clock Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Xianwei Zhao <xianwei.zhao@amlogic.com>

  - Jian Hu <jian.hu@amlogic.com>



properties:

  compatible:

    const: amlogic,t7-peripherals-clkc



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    minItems: 14

    items:

      - description: input oscillator

      - description: input sys clk

      - description: input fixed pll

      - description: input fclk div 2

      - description: input fclk div 2p5

      - description: input fclk div 3

      - description: input fclk div 4

      - description: input fclk div 5

      - description: input fclk div 7

      - description: input hifi pll

      - description: input gp0 pll

      - description: input gp1 pll

      - description: input mpll1

      - description: input mpll2

      - description: external input rmii oscillator (optional)

      - description: input video pll0 (optional)

      - description: external pad input for rtc (optional)



  clock-names:

    minItems: 14

    items:

      - const: xtal

      - const: sys

      - const: fix

      - const: fdiv2

      - const: fdiv2p5

      - const: fdiv3

      - const: fdiv4

      - const: fdiv5

      - const: fdiv7

      - const: hifi

      - const: gp0

      - const: gp1

      - const: mpll1

      - const: mpll2

      - const: ext_rmii

      - const: vid_pll0

      - const: ext_rtc



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



additionalProperties: false



examples:

  - |

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clkc_periphs:clock-controller@0 {

            compatible = "amlogic,t7-peripherals-clkc";

            reg = <0 0x0 0 0x1c8>;

            #clock-cells = <1>;

            clocks = <&xtal>,

                     <&scmi_clk 13>,

                     <&scmi_clk 16>,

                     <&scmi_clk 18>,

                     <&scmi_clk 20>,

                     <&scmi_clk 22>,

                     <&scmi_clk 24>,

                     <&scmi_clk 26>,

                     <&scmi_clk 28>,

                     <&hifi 1>,

                     <&gp0 1>,

                     <&gp1 1>,

                     <&mpll 4>,

                     <&mpll 6>;

            clock-names = "xtal",

                          "sys",

                          "fix",

                          "fdiv2",

                          "fdiv2p5",

                          "fdiv3",

                          "fdiv4",

                          "fdiv5",

                          "fdiv7",

                          "hifi",

                          "gp0",

                          "gp1",

                          "mpll1",

                          "mpll2";

        };

    };

Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic T7 PLL Clock Control Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>

  - Jerome Brunet <jbrunet@baylibre.com>

  - Jian Hu <jian.hu@amlogic.com>

  - Xianwei Zhao <xianwei.zhao@amlogic.com>



properties:

  compatible:

    enum:

      - amlogic,t7-gp0-pll

      - amlogic,t7-gp1-pll

      - amlogic,t7-hifi-pll

      - amlogic,t7-pcie-pll

      - amlogic,t7-mpll

      - amlogic,t7-hdmi-pll

      - amlogic,t7-mclk-pll



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: mclk pll input oscillator gate

      - description: oscillator input clock source for mclk_sel_0

      - description: fixed input clock source for mclk_sel_0

    minItems: 1



  clock-names:

    items:

      - const: in0

      - const: in1

      - const: in2

    minItems: 1



required:

  - compatible

  - '#clock-cells'

  - reg

  - clocks

  - clock-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: amlogic,t7-mclk-pll



    then:

      properties:

        clocks:

          minItems: 3



        clock-names:

          minItems: 3



  - if:

      properties:

        compatible:

          contains:

            enum:

              - amlogic,t7-gp0-pll

              - amlogic,t7-gp1--pll

              - amlogic,t7-hifi-pll

              - amlogic,t7-pcie-pll

              - amlogic,t7-mpll

              - amlogic,t7-hdmi-pll



    then:

      properties:

        clocks:

          maxItems: 1



        clock-names:

          maxItems: 1



additionalProperties: false



examples:

  - |

    apb {

        #address-cells = <2>;

        #size-cells = <2>;



        clock-controller@8080 {

            compatible = "amlogic,t7-gp0-pll";

            reg = <0 0x8080 0 0x20>;

            clocks = <&scmi_clk 2>;

            clock-names = "in0";

            #clock-cells = <1>;

        };



        clock-controller@8300 {

            compatible = "amlogic,t7-mclk-pll";

            reg = <0 0x8300 0 0x18>;

            clocks = <&scmi_clk 2>,

                     <&xtal>,

                     <&scmi_clk 31>;

            clock-names = "in0", "in1", "in2";

            #clock-cells = <1>;

        };

    };

drivers/clk/meson/Kconfig

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@@ -201,4 +201,32 @@ config COMMON_CLK_S4_PERIPHERALS 
	help

	  Support for the peripherals clock controller on Amlogic S805X2 and S905Y4

	  devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.



config COMMON_CLK_T7_PLL

	tristate "Amlogic T7 SoC PLL controller support"

	depends on ARM64

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PLL

	imply COMMON_CLK_SCMI

	help

	  Support for the PLL clock controller on Amlogic A311D2 based

	  device, AKA T7. PLLs are required by most peripheral to operate.

	  Say Y if you want T7 PLL clock controller to work.



config COMMON_CLK_T7_PERIPHERALS

	tristate "Amlogic T7 SoC peripherals clock controller support"

	depends on ARM64

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_DUALDIV

	imply COMMON_CLK_SCMI

	imply COMMON_CLK_T7_PLL

	help

	  Support for the peripherals clock controller on Amlogic A311D2 based

	  device, AKA T7. Peripherals are required by most peripheral to operate.

	  Say Y if you want T7 peripherals clock controller to work.

endmenu

drivers/clk/meson/Makefile

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@@ -26,3 +26,5 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o 
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o

obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o

obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o

obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o

drivers/clk/meson/g12a.c

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@@ -777,12 +777,23 @@ static struct clk_regmap g12a_hdmi_pll_dco = { 
	},

};



/*

 * G12/SM1 hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.

 * A divider value of 3 should map to /8 but instead map /4 so ignore it.

 */

static const struct clk_div_table g12a_hdmi_pll_od_div_table[] = {

	{ .val = 0, .div = 1 },

	{ .val = 1, .div = 2 },

	{ .val = 2, .div = 4 },

	{ /* sentinel */ }

};



static struct clk_regmap g12a_hdmi_pll_od = {

	.data = &(struct clk_regmap_div_data){

		.offset = HHI_HDMI_PLL_CNTL0,

		.shift = 16,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

		.table = g12a_hdmi_pll_od_div_table,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hdmi_pll_od",
@@ -800,7 +811,7 @@ static struct clk_regmap g12a_hdmi_pll_od2 = { 
		.offset = HHI_HDMI_PLL_CNTL0,

		.shift = 18,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

		.table = g12a_hdmi_pll_od_div_table,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hdmi_pll_od2",
@@ -818,7 +829,7 @@ static struct clk_regmap g12a_hdmi_pll = { 
		.offset = HHI_HDMI_PLL_CNTL0,

		.shift = 20,

		.width = 2,

		.flags = CLK_DIVIDER_POWER_OF_TWO,

		.table = g12a_hdmi_pll_od_div_table,

	},

	.hw.init = &(struct clk_init_data){

		.name = "hdmi_pll",