dt-bindings: memory: tegra20: mc: Convert to schema

NVIDIA Tegra20 MC(Memory Controller)

Required properties:

- compatible : "nvidia,tegra20-mc-gart"

- reg : Should contain 2 register ranges: physical base address and length of

  the controller's registers and the GART aperture respectively.

- clocks: Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

- clock-names: Must include the following entries:

  - mc: the module's clock input

- interrupts : Should contain MC General interrupt.

- #reset-cells : Should be 1. This cell represents memory client module ID.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>

  or in the TRM documentation.

- #iommu-cells: Should be 0. This cell represents the number of cells in an

  IOMMU specifier needed to encode an address. GART supports only a single

  address space that is shared by all devices, therefore no additional

  information needed for the address encoding.

- #interconnect-cells : Should be 1. This cell represents memory client.

  The assignments may be found in header file <dt-bindings/memory/tegra20-mc.h>.

Example:

	mc: memory-controller@7000f000 {

		compatible = "nvidia,tegra20-mc-gart";

		reg = <0x7000f000 0x400		/* controller registers */

		       0x58000000 0x02000000>;	/* GART aperture */

		clocks = <&tegra_car TEGRA20_CLK_MC>;

		clock-names = "mc";

		interrupts = <GIC_SPI 77 0x04>;

		#reset-cells = <1>;

		#iommu-cells = <0>;

		#interconnect-cells = <1>;

	};

	video-codec@6001a000 {

		compatible = "nvidia,tegra20-vde";

		...

		resets = <&mc TEGRA20_MC_RESET_VDE>;

		iommus = <&mc>;

	};

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NVIDIA Tegra20 SoC Memory Controller

maintainers:

  - Dmitry Osipenko <digetx@gmail.com>

  - Jon Hunter <jonathanh@nvidia.com>

  - Thierry Reding <thierry.reding@gmail.com>

description: |

  The Tegra20 Memory Controller merges request streams from various client

  interfaces into request stream(s) for the various memory target devices,

  and returns response data to the various clients. The Memory Controller

  has a configurable arbitration algorithm to allow the user to fine-tune

  performance among the various clients.

  Tegra20 Memory Controller includes the GART (Graphics Address Relocation

  Table) which allows Memory Controller to provide a linear view of a

  fragmented memory pages.

properties:

  compatible:

    const: nvidia,tegra20-mc-gart

  reg:

    items:

      - description: controller registers

      - description: GART registers

  clocks:

    maxItems: 1

  clock-names:

    items:

      - const: mc

  interrupts:

    maxItems: 1

  "#reset-cells":

    const: 1

  "#iommu-cells":

    const: 0

  "#interconnect-cells":

    const: 1

required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - "#reset-cells"

  - "#iommu-cells"

  - "#interconnect-cells"

additionalProperties: false

examples:

  - |

    memory-controller@7000f000 {

        compatible = "nvidia,tegra20-mc-gart";

        reg = <0x7000f000 0x400>,	/* Controller registers */

              <0x58000000 0x02000000>;	/* GART aperture */

        clocks = <&clock_controller 32>;

        clock-names = "mc";

        interrupts = <0 77 4>;

        #iommu-cells = <0>;

        #reset-cells = <1>;

        #interconnect-cells = <1>;

    };