Commit d8d78a90 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpuid updates from Borislav Petkov:

 - Add a feature flag which denotes AMD CPUs supporting workload
   classification with the purpose of using such hints when making
   scheduling decisions

 - Determine the boost enumerator for each AMD core based on its type:
   efficiency or performance, in the cppc driver

 - Add the type of a CPU to the topology CPU descriptor with the goal of
   supporting and making decisions based on the type of the respective
   core

 - Add a feature flag to denote AMD cores which have heterogeneous
   topology and enable SD_ASYM_PACKING for those

 - Check microcode revisions before disabling PCID on Intel

 - Cleanups and fixlets

* tag 'x86_cpu_for_v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpu: Remove redundant CONFIG_NUMA guard around numa_add_cpu()
  x86/cpu: Fix FAM5_QUARK_X1000 to use X86_MATCH_VFM()
  x86/cpu: Fix formatting of cpuid_bits[] in scattered.c
  x86/cpufeatures: Add X86_FEATURE_AMD_WORKLOAD_CLASS feature bit
  x86/amd: Use heterogeneous core topology for identifying boost numerator
  x86/cpu: Add CPU type to struct cpuinfo_topology
  x86/cpu: Enable SD_ASYM_PACKING for PKG domain on AMD
  x86/cpufeatures: Add X86_FEATURE_AMD_HETEROGENEOUS_CORES
  x86/cpufeatures: Rename X86_FEATURE_FAST_CPPC to have AMD prefix
  x86/mm: Don't disable PCID when INVLPG has been fixed by microcode
parents 55db8eb4 f74642d8

arch/x86/include/asm/cpufeatures.h

+3 −1
Original line number Diff line number Diff line
@@ -473,7 +473,9 @@ 
#define X86_FEATURE_BHI_CTRL		(21*32+ 2) /* BHI_DIS_S HW control available */

#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* Clear branch history at vmexit using SW loop */

#define X86_FEATURE_FAST_CPPC		(21*32 + 5) /* AMD Fast CPPC */

#define X86_FEATURE_AMD_FAST_CPPC	(21*32 + 5) /* Fast CPPC */

#define X86_FEATURE_AMD_HETEROGENEOUS_CORES (21*32 + 6) /* Heterogeneous Core Topology */

#define X86_FEATURE_AMD_WORKLOAD_CLASS	(21*32 + 7) /* Workload Classification */



/*

 * BUG word(s)

arch/x86/include/asm/intel-family.h

+6 −1
Original line number Diff line number Diff line
@@ -177,10 +177,15 @@ 
#define INTEL_XEON_PHI_KNM		IFM(6, 0x85) /* Knights Mill */



/* Family 5 */

#define INTEL_FAM5_QUARK_X1000		0x09 /* Quark X1000 SoC */

#define INTEL_QUARK_X1000		IFM(5, 0x09) /* Quark X1000 SoC */



/* Family 19 */

#define INTEL_PANTHERCOVE_X		IFM(19, 0x01) /* Diamond Rapids */



/* CPU core types */

enum intel_cpu_type {

	INTEL_CPU_TYPE_ATOM = 0x20,

	INTEL_CPU_TYPE_CORE = 0x40,

};



#endif /* _ASM_X86_INTEL_FAMILY_H */

arch/x86/include/asm/processor.h

+18 −0
Original line number Diff line number Diff line
@@ -105,6 +105,24 @@ struct cpuinfo_topology { 
	// Cache level topology IDs

	u32			llc_id;

	u32			l2c_id;



	// Hardware defined CPU-type

	union {

		u32		cpu_type;

		struct {

			// CPUID.1A.EAX[23-0]

			u32	intel_native_model_id	:24;

			// CPUID.1A.EAX[31-24]

			u32	intel_type		:8;

		};

		struct {

			// CPUID 0x80000026.EBX

			u32	amd_num_processors	:16,

				amd_power_eff_ranking	:8,

				amd_native_model_id	:4,

				amd_type		:4;

		};

	};

};



struct cpuinfo_x86 {

arch/x86/include/asm/topology.h

+9 −0
Original line number Diff line number Diff line
@@ -114,6 +114,12 @@ enum x86_topology_domains { 
	TOPO_MAX_DOMAIN,

};



enum x86_topology_cpu_type {

	TOPO_CPU_TYPE_PERFORMANCE,

	TOPO_CPU_TYPE_EFFICIENCY,

	TOPO_CPU_TYPE_UNKNOWN,

};



struct x86_topology_system {

	unsigned int	dom_shifts[TOPO_MAX_DOMAIN];

	unsigned int	dom_size[TOPO_MAX_DOMAIN];
@@ -149,6 +155,9 @@ extern unsigned int __max_threads_per_core; 
extern unsigned int __num_threads_per_package;

extern unsigned int __num_cores_per_package;



const char *get_topology_cpu_type_name(struct cpuinfo_x86 *c);

enum x86_topology_cpu_type get_topology_cpu_type(struct cpuinfo_x86 *c);



static inline unsigned int topology_max_packages(void)

{

	return __max_logical_packages;

arch/x86/kernel/acpi/cppc.c

+23 −0
Original line number Diff line number Diff line
@@ -239,8 +239,10 @@ EXPORT_SYMBOL_GPL(amd_detect_prefcore); 
 */

int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator)

{

	enum x86_topology_cpu_type core_type = get_topology_cpu_type(&cpu_data(cpu));

	bool prefcore;

	int ret;

	u32 tmp;



	ret = amd_detect_prefcore(&prefcore);

	if (ret)
@@ -266,6 +268,27 @@ int amd_get_boost_ratio_numerator(unsigned int cpu, u64 *numerator) 
			break;

		}

	}



	/* detect if running on heterogeneous design */

	if (cpu_feature_enabled(X86_FEATURE_AMD_HETEROGENEOUS_CORES)) {

		switch (core_type) {

		case TOPO_CPU_TYPE_UNKNOWN:

			pr_warn("Undefined core type found for cpu %d\n", cpu);

			break;

		case TOPO_CPU_TYPE_PERFORMANCE:

			/* use the max scale for performance cores */

			*numerator = CPPC_HIGHEST_PERF_PERFORMANCE;

			return 0;

		case TOPO_CPU_TYPE_EFFICIENCY:

			/* use the highest perf value for efficiency cores */

			ret = amd_get_highest_perf(cpu, &tmp);

			if (ret)

				return ret;

			*numerator = tmp;

			return 0;

		}

	}



	*numerator = CPPC_HIGHEST_PERF_PREFCORE;



	return 0;