Unverified Commit d8db5d8a authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'aspeed-5.17-devicetree' of... 

Merge tag 'aspeed-5.17-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt

ASPEED device tree updates for 5.17

 - New machines:

  * TYAN S8036 AST2500 BMC
  * Facebook Bletchley AST2600 BMC
  * Yadro VEGMAN series of AST2500 BMC for x86 servers

 - LPC clock additions, to fix long standing missed irq on boot issue

 - Secure boot controller description for AST2600

 - Alternate chip flash layout, used by Bytedance's G220A

 - Various additions to Rainier, Everest, S7106

* tag 'aspeed-5.17-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc

:
  ARM: dts: aspeed: add LCLK setting into LPC KCS nodes
  dt-bindings: ipmi: bt-bmc: add 'clocks' as a required property
  ARM: dts: aspeed: add LCLK setting into LPC IBT node
  ARM: dts: aspeed: p10: Add TPM device
  ARM: dts: aspeed: p10: Enable USB host ports
  ARM: dts: aspeed: Add TYAN S8036 BMC machine
  ARM: dts: aspeed: tyan-s7106: Add uart_routing and fix vuart config
  ARM: dts: aspeed: Adding Facebook Bletchley BMC
  ARM: dts: aspeed: g220a: Enable secondary flash
  ARM: dts: Add openbmc-flash-layout-64-alt.dtsi
  ARM: dts: aspeed: Add secure boot controller node
  dt-bindings: aspeed: Add Secure Boot Controller bindings
  ARM: dts: aspeed: add device tree for YADRO VEGMAN BMC
  dt-bindings: vendor-prefixes: add YADRO
  ARM: dts: aspeed: mtjade: Add uefi partition
  ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices
  ARM: dts: aspeed: tyan-s7106: Update nct7802 config

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 862d7e54 45cd8bba

Documentation/devicetree/bindings/arm/aspeed/aspeed,sbc.yaml

0 → 100644
+37 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)

# Copyright 2021 Joel Stanley, IBM Corp.

%YAML 1.2

---

$id: "http://devicetree.org/schemas/arm/aspeed/aspeed,sbc.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: ASPEED Secure Boot Controller



maintainers:

  - Joel Stanley <joel@jms.id.au>

  - Andrew Jeffery <andrew@aj.id.au>



description: |

  The ASPEED SoCs have a register bank for interacting with the secure boot

  controller.



properties:

  compatible:

    items:

      - const: aspeed,ast2600-sbc



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    sbc: secure-boot-controller@1e6f2000 {

            compatible = "aspeed,ast2600-sbc";

            reg = <0x1e6f2000 0x1000>;

    };

Documentation/devicetree/bindings/ipmi/aspeed,ast2400-ibt-bmc.txt

+2 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties: 
	"aspeed,ast2500-ibt-bmc"

	"aspeed,ast2600-ibt-bmc"

- reg: physical address and size of the registers

- clocks: clock for the device



Optional properties:
@@ -23,4 +24,5 @@ Example: 
		compatible = "aspeed,ast2400-ibt-bmc";

		reg = <0x1e789140 0x18>;

		interrupts = <8>;

		clocks = <&syscon ASPEED_CLK_GATE_LCLK>;

	};

Documentation/devicetree/bindings/vendor-prefixes.yaml

+2 −0
Original line number Diff line number Diff line
@@ -1356,6 +1356,8 @@ patternProperties: 
    description: Shenzhen Xunlong Software CO.,Limited

  "^xylon,.*":

    description: Xylon

  "^yadro,.*":

    description: YADRO

  "^yamaha,.*":

    description: Yamaha Corporation

  "^yes-optoelectronics,.*":

arch/arm/boot/dts/Makefile

+6 −1
Original line number Diff line number Diff line
@@ -1506,6 +1506,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ 
	aspeed-bmc-arm-stardragon4800-rep2.dtb \

	aspeed-bmc-asrock-e3c246d4i.dtb \

	aspeed-bmc-bytedance-g220a.dtb \

	aspeed-bmc-facebook-bletchley.dtb \

	aspeed-bmc-facebook-cloudripper.dtb \

	aspeed-bmc-facebook-cmm.dtb \

	aspeed-bmc-facebook-elbert.dtb \
@@ -1543,4 +1544,8 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ 
	aspeed-bmc-quanta-q71l.dtb \

	aspeed-bmc-supermicro-x11spi.dtb \

	aspeed-bmc-inventec-transformers.dtb \

	aspeed-bmc-tyan-s7106.dtb
 
	aspeed-bmc-tyan-s7106.dtb \

	aspeed-bmc-tyan-s8036.dtb \

	aspeed-bmc-vegman-n110.dtb \

	aspeed-bmc-vegman-rx20.dtb \

	aspeed-bmc-vegman-sx20.dtb

arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts

+267 −0
Original line number Diff line number Diff line
@@ -7,6 +7,50 @@ / { 
	model = "Ampere Mt. Jade BMC";

	compatible = "ampere,mtjade-bmc", "aspeed,ast2500";



	aliases {

		/*

		 *  i2c bus 50-57 assigned to NVMe slot 0-7

		 */

		i2c50 = &nvmeslot_0;

		i2c51 = &nvmeslot_1;

		i2c52 = &nvmeslot_2;

		i2c53 = &nvmeslot_3;

		i2c54 = &nvmeslot_4;

		i2c55 = &nvmeslot_5;

		i2c56 = &nvmeslot_6;

		i2c57 = &nvmeslot_7;



		/*

		 *  i2c bus 60-67 assigned to NVMe slot 8-15

		 */

		i2c60 = &nvmeslot_8;

		i2c61 = &nvmeslot_9;

		i2c62 = &nvmeslot_10;

		i2c63 = &nvmeslot_11;

		i2c64 = &nvmeslot_12;

		i2c65 = &nvmeslot_13;

		i2c66 = &nvmeslot_14;

		i2c67 = &nvmeslot_15;



		/*

		 *  i2c bus 70-77 assigned to NVMe slot 16-23

		 */

		i2c70 = &nvmeslot_16;

		i2c71 = &nvmeslot_17;

		i2c72 = &nvmeslot_18;

		i2c73 = &nvmeslot_19;

		i2c74 = &nvmeslot_20;

		i2c75 = &nvmeslot_21;

		i2c76 = &nvmeslot_22;

		i2c77 = &nvmeslot_23;



		/*

		 *  i2c bus 80-81 assigned to NVMe M2 slot 0-1

		 */

		i2c80 = &nvme_m2_0;

		i2c81 = &nvme_m2_1;

	};



	chosen {

		stdout-path = &uart5;

		bootargs = "console=ttyS4,115200 earlycon";
@@ -330,6 +374,15 @@ flash@0 { 
		m25p,fast-read;

		label = "pnor";

		/* spi-max-frequency = <100000000>; */

		partitions {

			compatible = "fixed-partitions";

			#address-cells = <1>;

			#size-cells = <1>;

			uefi@400000 {

				reg = <0x400000 0x1C00000>;

				label = "pnor-uefi";

			};

		};

	};

};
@@ -445,6 +498,220 @@ rtc@51 { 


&i2c5 {

	status = "okay";

	i2c-mux@70 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x70>;

		i2c-mux-idle-disconnect;



		nvmeslot_0_7: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x3>;

		};

	};



	i2c-mux@71 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x71>;

		i2c-mux-idle-disconnect;



		nvmeslot_8_15: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x4>;

		};



		nvmeslot_16_23: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x3>;

		};



	};



	i2c-mux@72 {

		compatible = "nxp,pca9545";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x72>;

		i2c-mux-idle-disconnect;



		nvme_m2_0: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x0>;

		};



		nvme_m2_1: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x1>;

		};

	};

};



&nvmeslot_0_7 {

	status = "okay";



	i2c-mux@75 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x75>;

		i2c-mux-idle-disconnect;



		nvmeslot_0: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x0>;

		};

		nvmeslot_1: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x1>;

		};

		nvmeslot_2: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x2>;

		};

		nvmeslot_3: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x3>;

		};

		nvmeslot_4: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x4>;

		};

		nvmeslot_5: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x5>;

		};

		nvmeslot_6: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x6>;

		};

		nvmeslot_7: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x7>;

		};



	};

};



&nvmeslot_8_15 {

	status = "okay";



	i2c-mux@75 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x75>;

		i2c-mux-idle-disconnect;



		nvmeslot_8: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x0>;

		};

		nvmeslot_9: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x1>;

		};

		nvmeslot_10: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x2>;

		};

		nvmeslot_11: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x3>;

		};

		nvmeslot_12: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x4>;

		};

		nvmeslot_13: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x5>;

		};

		nvmeslot_14: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x6>;

		};

		nvmeslot_15: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x7>;

		};

	};

};



&nvmeslot_16_23 {

	status = "okay";



	i2c-mux@75 {

		compatible = "nxp,pca9548";

		#address-cells = <1>;

		#size-cells = <0>;

		reg = <0x75>;

		i2c-mux-idle-disconnect;



		nvmeslot_16: i2c@0 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x0>;

		};

		nvmeslot_17: i2c@1 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x1>;

		};

		nvmeslot_18: i2c@2 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x2>;

		};

		nvmeslot_19: i2c@3 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x3>;

		};

		nvmeslot_20: i2c@4 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x4>;

		};

		nvmeslot_21: i2c@5 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x5>;

		};

		nvmeslot_22: i2c@6 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x6>;

		};

		nvmeslot_23: i2c@7 {

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x7>;

		};

	};

};



&i2c6 {