Commit d91a46d6 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 

Pull RISC-V fixes from Paul Walmsley:
 "The notable changes here are the three RISC-V timer compare register
  update sequence patches. These only apply to RV32 systems and are
  related to the 64-bit timer compare value being split across two
  separate 32-bit registers.

  We weren't using the appropriate three-write sequence, documented in
  the RISC-V ISA specifications, to avoid spurious timer interrupts
  during the update sequence; so, these patches now use the recommended
  sequence.

  This doesn't affect 64-bit RISC-V systems, since the timer compare
  value fits inside a single register and can be updated with a single
  write.

   - Fix the RISC-V timer compare register update sequence on RV32
     systems to use the recommended sequence in the RISC-V ISA manual

     This avoids spurious interrupts during updates

   - Add a dependence on the new CONFIG_CACHEMAINT_FOR_DMA Kconfig
     symbol for Renesas and StarFive RISC-V SoCs

   - Add a temporary workaround for a Clang compiler bug caused by using
     asm_goto_output for get_user()

   - Clarify our documentation to specifically state a particular ISA
     specification version for a chapter number reference"

* tag 'riscv-for-linus-6.19-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Add intermediate cast to 'unsigned long' in __get_user_asm
  riscv: Use 64-bit variable for output in __get_user_asm
  soc: renesas: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
  riscv: ERRATA_STARFIVE_JH7100: Fix missing dependency on new CONFIG_CACHEMAINT_FOR_DMA
  riscv: suspend: Fix stimecmp update hazard on RV32
  riscv: kvm: Fix vstimecmp update hazard on RV32
  riscv: clocksource: Fix stimecmp update hazard on RV32
  Documentation: riscv: uabi: Clarify ISA spec version for canonical order
parents d04ed417 841e47d5

Documentation/arch/riscv/uabi.rst

+3 −1
Original line number Diff line number Diff line
@@ -7,7 +7,9 @@ ISA string ordering in /proc/cpuinfo 
------------------------------------



The canonical order of ISA extension names in the ISA string is defined in

chapter 27 of the unprivileged specification.

Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA

(Document Version 20191213).



The specification uses vague wording, such as should, when it comes to ordering,

so for our purposes the following rules apply:

arch/riscv/Kconfig.errata

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ config ERRATA_STARFIVE_JH7100 
	select DMA_GLOBAL_POOL

	select RISCV_DMA_NONCOHERENT

	select RISCV_NONSTANDARD_CACHE_OPS

	select CACHEMAINT_FOR_DMA

	select SIFIVE_CCACHE

	default n

	help

arch/riscv/include/asm/uaccess.h

+12 −2
Original line number Diff line number Diff line
@@ -97,13 +97,23 @@ static inline unsigned long __untagged_addr_remote(struct mm_struct *mm, unsigne 
 */



#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT

/*

 * Use a temporary variable for the output of the asm goto to avoid a

 * triggering an LLVM assertion due to sign extending the output when

 * it is used in later function calls:

 * https://github.com/llvm/llvm-project/issues/143795

 */

#define __get_user_asm(insn, x, ptr, label)			\

do {								\

	u64 __tmp;						\

	asm_goto_output(					\

		"1:\n"						\

		"	" insn " %0, %1\n"			\

		_ASM_EXTABLE_UACCESS_ERR(1b, %l2, %0)		\

		: "=&r" (x)					\

		: "m" (*(ptr)) : : label)

		: "=&r" (__tmp)					\

		: "m" (*(ptr)) : : label);			\

	(x) = (__typeof__(x))(unsigned long)__tmp;		\

} while (0)

#else /* !CONFIG_CC_HAS_ASM_GOTO_OUTPUT */

#define __get_user_asm(insn, x, ptr, label)			\

do {								\

arch/riscv/kernel/suspend.c

+2 −1
Original line number Diff line number Diff line
@@ -51,10 +51,11 @@ void suspend_restore_csrs(struct suspend_context *context) 


#ifdef CONFIG_MMU

	if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SSTC)) {

		csr_write(CSR_STIMECMP, context->stimecmp);

#if __riscv_xlen < 64

		csr_write(CSR_STIMECMP, ULONG_MAX);

		csr_write(CSR_STIMECMPH, context->stimecmph);

#endif

		csr_write(CSR_STIMECMP, context->stimecmp);

	}



	csr_write(CSR_SATP, context->satp);

arch/riscv/kvm/vcpu_timer.c

+4 −2
Original line number Diff line number Diff line
@@ -72,8 +72,9 @@ static int kvm_riscv_vcpu_timer_cancel(struct kvm_vcpu_timer *t) 
static int kvm_riscv_vcpu_update_vstimecmp(struct kvm_vcpu *vcpu, u64 ncycles)

{

#if defined(CONFIG_32BIT)

	ncsr_write(CSR_VSTIMECMP, ncycles & 0xFFFFFFFF);

	ncsr_write(CSR_VSTIMECMP,  ULONG_MAX);

	ncsr_write(CSR_VSTIMECMPH, ncycles >> 32);

	ncsr_write(CSR_VSTIMECMP, (u32)ncycles);

#else

	ncsr_write(CSR_VSTIMECMP, ncycles);

#endif
@@ -307,8 +308,9 @@ void kvm_riscv_vcpu_timer_restore(struct kvm_vcpu *vcpu) 
		return;



#if defined(CONFIG_32BIT)

	ncsr_write(CSR_VSTIMECMP, (u32)t->next_cycles);

	ncsr_write(CSR_VSTIMECMP, ULONG_MAX);

	ncsr_write(CSR_VSTIMECMPH, (u32)(t->next_cycles >> 32));

	ncsr_write(CSR_VSTIMECMP, (u32)(t->next_cycles));

#else

	ncsr_write(CSR_VSTIMECMP, t->next_cycles);

#endif