Commit d92df66f authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/psr: Implement Wa 14019834836 



This patch implements HW workaround 14019834836 for display version 30.

v2:
  - move Wa 14019834836 to it's own function
  - apply only for display version 30

Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240926064759.1313335-3-jouni.hogander@intel.com
parent f3c25031

drivers/gpu/drm/i915/display/intel_psr.c

+36 −0
Original line number Diff line number Diff line
@@ -2519,6 +2519,38 @@ static bool psr2_sel_fetch_pipe_state_supported(const struct intel_crtc_state *c 
	return true;

}



/* Wa 14019834836 */

static void intel_psr_apply_pr_link_on_su_wa(struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(crtc_state);

	struct intel_encoder *encoder;

	int hactive_limit;



	if (crtc_state->psr2_su_area.y1 != 0 ||

	    crtc_state->psr2_su_area.y2 != 0)

		return;



	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

		hactive_limit = intel_dp_is_uhbr(crtc_state) ? 1230 : 546;

	else

		hactive_limit = intel_dp_is_uhbr(crtc_state) ? 615 : 273;



	if (crtc_state->hw.adjusted_mode.hdisplay < hactive_limit)

		return;



	for_each_intel_encoder_mask_with_psr(display->drm, encoder,

					     crtc_state->uapi.encoder_mask) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		if (!intel_dp_is_edp(intel_dp) &&

		    intel_dp->psr.panel_replay_enabled &&

		    intel_dp->psr.sel_update_enabled) {

			crtc_state->psr2_su_area.y2++;

			return;

		}

	}

}



static void

intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)

{
@@ -2531,6 +2563,10 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state) 
	      IS_ALDERLAKE_P(i915) || IS_TIGERLAKE(i915))) &&

	    crtc_state->splitter.enable)

		crtc_state->psr2_su_area.y1 = 0;



	/* Wa 14019834836 */

	if (DISPLAY_VER(display) == 30)

		intel_psr_apply_pr_link_on_su_wa(crtc_state);

}



int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,