Unverified Commit d9708b19 authored by Guo Ren's avatar Guo Ren Committed by Alexandre Ghiti
Browse files

riscv: Implement smp_cond_load8/16() with Zawrs 



RISC-V code uses the queued spinlock implementation, which calls
the macros smp_cond_load_acquire for one byte. So, complement the
implementation of byte and halfword versions.

Signed-off-by: default avatarGuo Ren <guoren@linux.alibaba.com>
Signed-off-by: default avatarGuo Ren <guoren@kernel.org>
Cc: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20241217013910.1039923-1-guoren@kernel.org


Signed-off-by: default avatarAlexandre Ghiti <alexghiti@rivosinc.com>
parent d9be2b9b

arch/riscv/include/asm/cmpxchg.h

+35 −3
Original line number Diff line number Diff line
@@ -365,16 +365,48 @@ static __always_inline void __cmpwait(volatile void *ptr, 
{

	unsigned long tmp;



	u32 *__ptr32b;

	ulong __s, __val, __mask;



	asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop",

			     0, RISCV_ISA_EXT_ZAWRS, 1)

		 : : : : no_zawrs);



	switch (size) {

	case 1:

		fallthrough;

		__ptr32b = (u32 *)((ulong)(ptr) & ~0x3);

		__s = ((ulong)(ptr) & 0x3) * BITS_PER_BYTE;

		__val = val << __s;

		__mask = 0xff << __s;



		asm volatile(

		"	lr.w	%0, %1\n"

		"	and	%0, %0, %3\n"

		"	xor	%0, %0, %2\n"

		"	bnez	%0, 1f\n"

			ZAWRS_WRS_NTO "\n"

		"1:"

		: "=&r" (tmp), "+A" (*(__ptr32b))

		: "r" (__val), "r" (__mask)

		: "memory");

		break;

	case 2:

		/* RISC-V doesn't have lr instructions on byte and half-word. */

		goto no_zawrs;

		__ptr32b = (u32 *)((ulong)(ptr) & ~0x3);

		__s = ((ulong)(ptr) & 0x2) * BITS_PER_BYTE;

		__val = val << __s;

		__mask = 0xffff << __s;



		asm volatile(

		"	lr.w	%0, %1\n"

		"	and	%0, %0, %3\n"

		"	xor	%0, %0, %2\n"

		"	bnez	%0, 1f\n"

			ZAWRS_WRS_NTO "\n"

		"1:"

		: "=&r" (tmp), "+A" (*(__ptr32b))

		: "r" (__val), "r" (__mask)

		: "memory");

		break;

	case 4:

		asm volatile(

		"	lr.w	%0, %1\n"