Commit d9864e7d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 perf fix from Thomas Gleixner:
 "A single fix for the x86 performance counters on Intel CPUs:

  The MSR offset calculations for fixed performance counters are stored
  at the wrong index in the configuration array causing the general
  purpose counter MSR offset to be overwritten, so both the general
  purpose and the fixed counters offsets are incorrect.

  Correct the array index calculation to fix that"

* tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config_acr()
parents 70b7d651 86aa94cd

arch/x86/events/intel/core.c

+5 −3
Original line number Diff line number Diff line
@@ -2900,6 +2900,7 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 
{

	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);

	int msr_b, msr_c;

	int msr_offset;



	if (!mask && !cpuc->acr_cfg_b[idx])

		return;
@@ -2907,19 +2908,20 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload) 
	if (idx < INTEL_PMC_IDX_FIXED) {

		msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;

		msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;

		msr_offset = x86_pmu.addr_offset(idx, false);

	} else {

		msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;

		msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;

		idx -= INTEL_PMC_IDX_FIXED;

		msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);

	}



	if (cpuc->acr_cfg_b[idx] != mask) {

		wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask);

		wrmsrl(msr_b + msr_offset, mask);

		cpuc->acr_cfg_b[idx] = mask;

	}

	/* Only need to update the reload value when there is a valid config value. */

	if (mask && cpuc->acr_cfg_c[idx] != reload) {

		wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload);

		wrmsrl(msr_c + msr_offset, reload);

		cpuc->acr_cfg_c[idx] = reload;

	}

}