Commit d9bf944b authored by Sam Shih's avatar Sam Shih Committed by Stephen Boyd
Browse files

clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 



Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: default avatarSam Shih <sam.shih@mediatek.com>
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent afd36e9d

drivers/clk/mediatek/clk-pll.c

+3 −2
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#define CON0_BASE_EN		BIT(0)

#define CON0_PWR_ON		BIT(0)

#define CON0_ISO_EN		BIT(1)

#define PCW_CHG_MASK		BIT(31)

#define PCW_CHG_BIT		31



#define AUDPLL_TUNER_EN		BIT(31)
@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, 
			pll->data->pcw_shift);

	val |= pcw << pll->data->pcw_shift;

	writel(val, pll->pcw_addr);

	chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;

	chg = readl(pll->pcw_chg_addr) |

	      BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);

	writel(chg, pll->pcw_chg_addr);

	if (pll->tuner_addr)

		writel(val + 1, pll->tuner_addr);

drivers/clk/mediatek/clk-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ struct mtk_pll_data { 
	const char *parent_name;

	u32 en_reg;

	u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */

	u8 pcw_chg_bit;

};



/*