Unverified Commit d9e33b38 authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Mark Brown
Browse files

spi: cadence-quadspi: Use BIT() macros where possible 



Convert few open coded bit shifts to BIT() macro for better readability.
No functional changes intended.

Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: default avatarSanthosh Kumar K <s-k6@ti.com>
Message-ID: <20250905185958.3575037-5-s-k6@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 858d4d9e

drivers/spi/spi-cadence-quadspi.c

+8 −8
Original line number Diff line number Diff line
@@ -335,7 +335,7 @@ static bool cqspi_is_idle(struct cqspi_st *cqspi) 
{

	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);



	return reg & (1UL << CQSPI_REG_CONFIG_IDLE_LSB);

	return reg & BIT(CQSPI_REG_CONFIG_IDLE_LSB);

}



static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
@@ -571,7 +571,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 
		reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)

		     << CQSPI_REG_CMDCTRL_DUMMY_LSB;



	reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);

	reg |= BIT(CQSPI_REG_CMDCTRL_RD_EN_LSB);



	/* 0 means 1 byte. */

	reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
@@ -579,7 +579,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, 


	/* setup ADDR BIT field */

	if (op->addr.nbytes) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= ((op->addr.nbytes - 1) &

			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
@@ -646,7 +646,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 
	reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;



	if (op->addr.nbytes) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_ADDR_EN_LSB);

		reg |= ((op->addr.nbytes - 1) &

			CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
@@ -655,7 +655,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, 
	}



	if (n_tx) {

		reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);

		reg |= BIT(CQSPI_REG_CMDCTRL_WR_EN_LSB);

		reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)

			<< CQSPI_REG_CMDCTRL_WR_BYTES_LSB;

		data = 0;
@@ -1191,7 +1191,7 @@ static void cqspi_chipselect(struct cqspi_flash_pdata *f_pdata) 
		 * CS2 to 4b'1011

		 * CS3 to 4b'0111

		 */

		chip_select = 0xF & ~(1 << chip_select);

		chip_select = 0xF & ~BIT(chip_select);

	}



	reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
@@ -1277,9 +1277,9 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, 
	reg = readl(reg_base + CQSPI_REG_READCAPTURE);



	if (bypass)

		reg |= (1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);

		reg |= BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);

	else

		reg &= ~(1 << CQSPI_REG_READCAPTURE_BYPASS_LSB);

		reg &= ~BIT(CQSPI_REG_READCAPTURE_BYPASS_LSB);



	reg &= ~(CQSPI_REG_READCAPTURE_DELAY_MASK

		 << CQSPI_REG_READCAPTURE_DELAY_LSB);