Commit d9fb08ba authored by Catalin Marinas's avatar Catalin Marinas
Browse files

arm64: tlb: Pass the corresponding mm to __tlbi_sync_s1ish() 



The mm structure will be used for workarounds that need limiting to
specific tasks.

Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6bfbf574

arch/arm64/include/asm/tlbflush.h

+4 −4
Original line number Diff line number Diff line
@@ -185,7 +185,7 @@ do { \ 
 * Complete broadcast TLB maintenance issued by the host which invalidates

 * stage 1 information in the host's own translation regime.

 */

static inline void __tlbi_sync_s1ish(void)

static inline void __tlbi_sync_s1ish(struct mm_struct *mm)

{

	dsb(ish);

	__repeat_tlbi_sync(vale1is, 0);
@@ -323,7 +323,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm) 
	asid = __TLBI_VADDR(0, ASID(mm));

	__tlbi(aside1is, asid);

	__tlbi_user(aside1is, asid);

	__tlbi_sync_s1ish();

	__tlbi_sync_s1ish(mm);

	mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);

}
@@ -377,7 +377,7 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, 
				  unsigned long uaddr)

{

	flush_tlb_page_nosync(vma, uaddr);

	__tlbi_sync_s1ish();

	__tlbi_sync_s1ish(vma->vm_mm);

}



static inline bool arch_tlbbatch_should_defer(struct mm_struct *mm)
@@ -532,7 +532,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, 
{

	__flush_tlb_range_nosync(vma->vm_mm, start, end, stride,

				 last_level, tlb_level);

	__tlbi_sync_s1ish();

	__tlbi_sync_s1ish(vma->vm_mm);

}



static inline void local_flush_tlb_contpte(struct vm_area_struct *vma,

arch/arm64/kernel/sys_compat.c

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ __do_compat_cache_op(unsigned long start, unsigned long end) 
			 * We pick the reserved-ASID to minimise the impact.

			 */

			__tlbi(aside1is, __TLBI_VADDR(0, 0));

			__tlbi_sync_s1ish();

			__tlbi_sync_s1ish(current->mm);

		}



		ret = caches_clean_inval_user_pou(start, start + chunk);