Commit da120ed5 authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
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drm/amdgpu: Per-instance init func for JPEG5_0_1 



Add helper functions to handle per-instance and per-core
initialization and deinitialization in JPEG5_0_1.

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a1addcf8

drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c

+69 −81
Original line number Diff line number Diff line
@@ -326,11 +326,10 @@ static int jpeg_v5_0_1_resume(struct amdgpu_ip_block *ip_block) 
	return r;

}



static int jpeg_v5_0_1_disable_antihang(struct amdgpu_device *adev, int inst_idx)

static void jpeg_v5_0_1_init_inst(struct amdgpu_device *adev, int i)

{

	int jpeg_inst;

	int jpeg_inst = GET_INST(JPEG, i);



	jpeg_inst = GET_INST(JPEG, inst_idx);

	/* disable anti hang mechanism */

	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,

		 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
@@ -339,65 +338,45 @@ static int jpeg_v5_0_1_disable_antihang(struct amdgpu_device *adev, int inst_idx 
	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS), 0,

		 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);



	return 0;

	/* MJPEG global tiling registers */

	WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,

		     adev->gfx.config.gb_addr_config);



	/* enable JMI channel */

	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,

		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);

}



static int jpeg_v5_0_1_enable_antihang(struct amdgpu_device *adev, int inst_idx)

static void jpeg_v5_0_1_deinit_inst(struct amdgpu_device *adev, int i)

{

	int jpeg_inst;

	int jpeg_inst = GET_INST(JPEG, i);

	/* reset JMI */

	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),

		 UVD_JMI_CNTL__SOFT_RESET_MASK,

		 ~UVD_JMI_CNTL__SOFT_RESET_MASK);



	jpeg_inst = GET_INST(JPEG, inst_idx);

	/* enable anti hang mechanism */

	WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JPEG_POWER_STATUS),

		 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,

		 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);



	return 0;

}



/**

 * jpeg_v5_0_1_start - start JPEG block

 *

 * @adev: amdgpu_device pointer

 *

 * Setup and start the JPEG block

 */

static int jpeg_v5_0_1_start(struct amdgpu_device *adev)

static void jpeg_v5_0_1_init_jrbc(struct amdgpu_ring *ring)

{

	struct amdgpu_ring *ring;

	int i, j, jpeg_inst, r;



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		jpeg_inst = GET_INST(JPEG, i);



		/* disable antihang */

		r = jpeg_v5_0_1_disable_antihang(adev, i);

		if (r)

			return r;



		/* MJPEG global tiling registers */

		WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,

			     adev->gfx.config.gb_addr_config);



		/* enable JMI channel */

		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL), 0,

			 ~UVD_JMI_CNTL__SOFT_RESET_MASK);



		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {

			int reg_offset = (j ? jpeg_v5_0_1_core_reg_offset(j) : 0);

	struct amdgpu_device *adev = ring->adev;

	u32 reg, data, mask;



			ring = &adev->jpeg.inst[i].ring_dec[j];

	int jpeg_inst = GET_INST(JPEG, ring->me);

	int reg_offset = ring->pipe ? jpeg_v5_0_1_core_reg_offset(ring->pipe) : 0;



	/* enable System Interrupt for JRBC */

	reg = SOC15_REG_OFFSET(JPEG, jpeg_inst, regJPEG_SYS_INT_EN);

			if (j < AMDGPU_MAX_JPEG_RINGS_4_0_3) {

				data = JPEG_SYS_INT_EN__DJRBC0_MASK << j;

				mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << j);

	if (ring->pipe < AMDGPU_MAX_JPEG_RINGS_4_0_3) {

		data = JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe;

		mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << ring->pipe);

		WREG32_P(reg, data, mask);

	} else {

				data = JPEG_SYS_INT_EN__DJRBC0_MASK << (j+12);

				mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (j+12));

		data = JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12);

		mask = ~(JPEG_SYS_INT_EN__DJRBC0_MASK << (ring->pipe+12));

		WREG32_P(reg, data, mask);

	}
@@ -429,6 +408,25 @@ static int jpeg_v5_0_1_start(struct amdgpu_device *adev) 
	ring->wptr = RREG32_SOC15_OFFSET(JPEG, jpeg_inst, regUVD_JRBC_RB_WPTR,

					 reg_offset);

}



/**

 * jpeg_v5_0_1_start - start JPEG block

 *

 * @adev: amdgpu_device pointer

 *

 * Setup and start the JPEG block

 */

static int jpeg_v5_0_1_start(struct amdgpu_device *adev)

{

	struct amdgpu_ring *ring;

	int i, j;



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		jpeg_v5_0_1_init_inst(adev, i);

		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {

			ring = &adev->jpeg.inst[i].ring_dec[j];

			jpeg_v5_0_1_init_jrbc(ring);

		}

	}



	return 0;
@@ -443,20 +441,10 @@ static int jpeg_v5_0_1_start(struct amdgpu_device *adev) 
 */

static int jpeg_v5_0_1_stop(struct amdgpu_device *adev)

{

	int i, jpeg_inst, r;



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		jpeg_inst = GET_INST(JPEG, i);

		/* reset JMI */

		WREG32_P(SOC15_REG_OFFSET(JPEG, jpeg_inst, regUVD_JMI_CNTL),

			 UVD_JMI_CNTL__SOFT_RESET_MASK,

			 ~UVD_JMI_CNTL__SOFT_RESET_MASK);

	int i;



		/* enable antihang */

		r = jpeg_v5_0_1_enable_antihang(adev, i);

		if (r)

			return r;

	}

	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i)

		jpeg_v5_0_1_deinit_inst(adev, i);



	return 0;

}