Commit da51bbcd authored by Remington Brasga's avatar Remington Brasga Committed by Jonathan Corbet
Browse files

Docs: typos/spelling 



Fix spelling and grammar in Docs descriptions

Signed-off-by: default avatarRemington Brasga <rbrasga@uci.edu>
Reviewed-by: default avatarRandy Dunlap <rdunlap@infradead.org>
Signed-off-by: default avatarJonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20240429225527.2329-1-rbrasga@uci.edu
parent d43ddd5c

Documentation/admin-guide/hw-vuln/srso.rst

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@@ -135,7 +135,7 @@ and does not want to suffer the performance impact, one can always 
disable the mitigation with spec_rstack_overflow=off.



Similarly, 'Mitigation: IBPB' is another full mitigation type employing

an indrect branch prediction barrier after having applied the required

an indirect branch prediction barrier after having applied the required

microcode patch for one's system. This mitigation comes also at

a performance cost.

Documentation/admin-guide/kernel-parameters.txt

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@@ -7308,7 +7308,7 @@ 
			This can be changed after boot by writing to the

			matching /sys/module/workqueue/parameters file. All

			workqueues with the "default" affinity scope will be

			updated accordignly.

			updated accordingly.



	workqueue.debug_force_rr_cpu

			Workqueue used to implicitly guarantee that work

Documentation/admin-guide/mm/ksm.rst

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@@ -308,7 +308,7 @@ limited by the ``advisor_max_cpu`` parameter. In addition there is also the 
``advisor_target_scan_time`` parameter. This parameter sets the target time to

scan all the KSM candidate pages. The parameter ``advisor_target_scan_time``

decides how aggressive the scan time advisor scans candidate pages. Lower

values make the scan time advisor to scan more aggresively. This is the most

values make the scan time advisor to scan more aggressively. This is the most

important parameter for the configuration of the scan time advisor.



The initial value and the maximum value can be changed with

Documentation/arch/m68k/buddha-driver.rst

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@@ -173,7 +173,7 @@ When accessing IDE registers with A6=1 (for example $84x), 
the timing will always be mode 0 8-bit compatible, no matter

what you have selected in the speed register:



781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.

781ns select, IOR/IOW after 4 clock cycles (=314ns) active.



All  the  timings with a very short select-signal (the 355ns

fast  accesses)  depend  on the accelerator card used in the

Documentation/arch/sparc/oradax/dax-hv-api.txt

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@@ -41,7 +41,7 @@ Chapter 36. Coprocessor services 
        submissions until they succeed; waiting for an outstanding CCB to complete is not necessary, and would

        not be a guarantee that a future submission would succeed.



        The availablility of DAX coprocessor command service is indicated by the presence of the DAX virtual

        The availability of DAX coprocessor command service is indicated by the presence of the DAX virtual

        device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device

        node”).