Commit da9af507 authored by Marc Zyngier's avatar Marc Zyngier Committed by Oliver Upton
Browse files

arm64: cpufeature: Detect HCR_EL2.NV1 being RES0 



A variant of FEAT_E2H0 not being implemented exists in the form of
HCR_EL2.E2H being RES1 *and* HCR_EL2.NV1 being RES0 (indicating that
only VHE is supported on the host and nested guests).

Add the necessary infrastructure for this new CPU capability.

Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20240122181344.258974-7-maz@kernel.org


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 805bb61f

arch/arm64/kernel/cpufeature.c

+12 −0
Original line number Diff line number Diff line
@@ -1794,6 +1794,11 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 
	return !meltdown_safe;

}



static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope)

{

	return !has_cpuid_feature(entry, scope);

}



#if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2)

static bool has_lpa2_at_stage1(u64 mmfr0)

{
@@ -2794,6 +2799,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { 
		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_lpa2,

	},

	{

		.desc = "NV1",

		.capability = ARM64_HAS_HCR_NV1,

		.type = ARM64_CPUCAP_SYSTEM_FEATURE,

		.matches = has_nv1,

		ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1)

	},

	{},

};

arch/arm64/tools/cpucaps

+1 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ HAS_GENERIC_AUTH_IMP_DEF 
HAS_GIC_CPUIF_SYSREGS

HAS_GIC_PRIO_MASKING

HAS_GIC_PRIO_RELAXED_SYNC

HAS_HCR_NV1

HAS_HCX

HAS_LDAPR

HAS_LPA2