Commit dabf72b8 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Fix FOUTPOSTDIV clk 



While computing foutpostdiv_rate, the value of params->pl5_fracin
is discarded, which results in the wrong refresh rate. Fix the formula
for computing foutpostdiv_rate.

Fixes: 1561380e ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
Signed-off-by: default avatarHien Huynh <hien.huynh.px@renesas.com>
Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e200b06d

drivers/clk/renesas/rzg2l-cpg.c

+6 −5
Original line number Diff line number Diff line
@@ -548,7 +548,7 @@ static unsigned long 
rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,

			       unsigned long rate)

{

	unsigned long foutpostdiv_rate;

	unsigned long foutpostdiv_rate, foutvco_rate;



	params->pl5_intin = rate / MEGA;

	params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
@@ -557,10 +557,11 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params, 
	params->pl5_postdiv2 = 1;

	params->pl5_spread = 0x16;



	foutpostdiv_rate =

		EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv *

		((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) /

		(params->pl5_postdiv1 * params->pl5_postdiv2);

	foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,

					   (params->pl5_intin << 24) + params->pl5_fracin),

			       params->pl5_refdiv) >> 24;

	foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate,

						 params->pl5_postdiv1 * params->pl5_postdiv2);



	return foutpostdiv_rate;

}