Commit dac62bca authored by Tomi Valkeinen's avatar Tomi Valkeinen
Browse files

drm/omap: remove dispc_ops 



dispc_ops was created to help with the multi-module architecture and
giving us the possibility of multiple dispc implementations. Neither of
these is valid anymore, and we can remove dispc_ops and use direct
calls to dispc.

Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201215104657.802264-54-tomi.valkeinen@ti.com
parent 96f44185

drivers/gpu/drm/omapdrm/dss/base.c

+0 −5
Original line number Diff line number Diff line
@@ -21,11 +21,6 @@ struct dispc_device *dispc_get_dispc(struct dss_device *dss) 
	return dss->dispc;

}



const struct dispc_ops *dispc_get_ops(struct dss_device *dss)

{

	return dss->dispc_ops;

}



/* -----------------------------------------------------------------------------

 * OMAP DSS Devices Handling

 */

drivers/gpu/drm/omapdrm/dss/dispc.c

+28 −73
Original line number Diff line number Diff line
@@ -351,8 +351,6 @@ static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, 
static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,

					   enum omap_plane_id plane);



static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);



static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)

{

	__raw_writel(val, dispc->base + idx);
@@ -379,12 +377,12 @@ static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, 
	REG_FLD_MOD(dispc, rfld->reg, val, rfld->high, rfld->low);

}



static int dispc_get_num_ovls(struct dispc_device *dispc)

int dispc_get_num_ovls(struct dispc_device *dispc)

{

	return dispc->feat->num_ovls;

}



static int dispc_get_num_mgrs(struct dispc_device *dispc)

int dispc_get_num_mgrs(struct dispc_device *dispc)

{

	return dispc->feat->num_mgrs;

}
@@ -670,13 +668,13 @@ void dispc_runtime_put(struct dispc_device *dispc) 
	WARN_ON(r < 0 && r != -ENOSYS);

}



static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,

u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,

				   enum omap_channel channel)

{

	return mgr_desc[channel].vsync_irq;

}



static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,

u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,

				       enum omap_channel channel)

{

	if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv)
@@ -685,18 +683,18 @@ static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, 
	return mgr_desc[channel].framedone_irq;

}



static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,

u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,

				       enum omap_channel channel)

{

	return mgr_desc[channel].sync_lost_irq;

}



static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc)

u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc)

{

	return DISPC_IRQ_FRAMEDONEWB;

}



static void dispc_mgr_enable(struct dispc_device *dispc,

void dispc_mgr_enable(struct dispc_device *dispc,

			     enum omap_channel channel, bool enable)

{

	mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
@@ -710,13 +708,13 @@ static bool dispc_mgr_is_enabled(struct dispc_device *dispc, 
	return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);

}



static bool dispc_mgr_go_busy(struct dispc_device *dispc,

bool dispc_mgr_go_busy(struct dispc_device *dispc,

			      enum omap_channel channel)

{

	return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;

}



static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)

void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)

{

	WARN_ON(!dispc_mgr_is_enabled(dispc, channel));

	WARN_ON(dispc_mgr_go_busy(dispc, channel));
@@ -726,12 +724,12 @@ static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) 
	mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);

}



static bool dispc_wb_go_busy(struct dispc_device *dispc)

bool dispc_wb_go_busy(struct dispc_device *dispc)

{

	return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;

}



static void dispc_wb_go(struct dispc_device *dispc)

void dispc_wb_go(struct dispc_device *dispc)

{

	enum omap_plane_id plane = OMAP_DSS_WB;

	bool enable, go;
@@ -1297,7 +1295,7 @@ static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, 
	return false;

}



static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,

const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,

					    enum omap_plane_id plane)

{

	return dispc->feat->supported_color_modes[plane];
@@ -2781,7 +2779,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, 
	return 0;

}



static int dispc_ovl_setup(struct dispc_device *dispc,

int dispc_ovl_setup(struct dispc_device *dispc,

			   enum omap_plane_id plane,

			   const struct omap_overlay_info *oi,

			   const struct videomode *vm, bool mem_to_mem,
@@ -2809,7 +2807,7 @@ static int dispc_ovl_setup(struct dispc_device *dispc, 
	return r;

}



static int dispc_wb_setup(struct dispc_device *dispc,

int dispc_wb_setup(struct dispc_device *dispc,

		   const struct omap_dss_writeback_info *wi,

		   bool mem_to_mem, const struct videomode *vm,

		   enum dss_writeback_channel channel_in)
@@ -2893,12 +2891,12 @@ static int dispc_wb_setup(struct dispc_device *dispc, 
	return 0;

}



static bool dispc_has_writeback(struct dispc_device *dispc)

bool dispc_has_writeback(struct dispc_device *dispc)

{

	return dispc->feat->has_writeback;

}



static int dispc_ovl_enable(struct dispc_device *dispc,

int dispc_ovl_enable(struct dispc_device *dispc,

			    enum omap_plane_id plane, bool enable)

{

	DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
@@ -2989,7 +2987,7 @@ static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, 
		REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);

}



static void dispc_mgr_setup(struct dispc_device *dispc,

void dispc_mgr_setup(struct dispc_device *dispc,

			    enum omap_channel channel,

			    const struct omap_overlay_manager_info *info)

{
@@ -3068,7 +3066,7 @@ static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, 
	mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);

}



static void dispc_mgr_set_lcd_config(struct dispc_device *dispc,

void dispc_mgr_set_lcd_config(struct dispc_device *dispc,

				     enum omap_channel channel,

				     const struct dss_lcd_mgr_config *config)

{
@@ -3117,7 +3115,7 @@ static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, 
		return pclk <= dispc->feat->max_tv_pclk;

}



static int dispc_mgr_check_timings(struct dispc_device *dispc,

int dispc_mgr_check_timings(struct dispc_device *dispc,

				   enum omap_channel channel,

				   const struct videomode *vm)

{
@@ -3210,7 +3208,7 @@ static int vm_flag_to_int(enum display_flags flags, enum display_flags high, 
}



/* change name to mode? */

static void dispc_mgr_set_timings(struct dispc_device *dispc,

void dispc_mgr_set_timings(struct dispc_device *dispc,

				  enum omap_channel channel,

				  const struct videomode *vm)

{
@@ -3754,17 +3752,17 @@ int dispc_mgr_get_clock_div(struct dispc_device *dispc, 
	return 0;

}



static u32 dispc_read_irqstatus(struct dispc_device *dispc)

u32 dispc_read_irqstatus(struct dispc_device *dispc)

{

	return dispc_read_reg(dispc, DISPC_IRQSTATUS);

}



static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask)

void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask)

{

	dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);

}



static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask)

void dispc_write_irqenable(struct dispc_device *dispc, u32 mask)

{

	u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE);
@@ -3788,7 +3786,7 @@ void dispc_disable_sidle(struct dispc_device *dispc) 
	REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3);	/* SIDLEMODE: no idle */

}



static u32 dispc_mgr_gamma_size(struct dispc_device *dispc,

u32 dispc_mgr_gamma_size(struct dispc_device *dispc,

				enum omap_channel channel)

{

	const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
@@ -3843,7 +3841,7 @@ static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 
	{ .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },

};



static void dispc_mgr_set_gamma(struct dispc_device *dispc,

void dispc_mgr_set_gamma(struct dispc_device *dispc,

				enum omap_channel channel,

				const struct drm_color_lut *lut,

				unsigned int length)
@@ -4499,7 +4497,7 @@ static irqreturn_t dispc_irq_handler(int irq, void *arg) 
	return dispc->user_handler(irq, dispc->user_data);

}



static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,

int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,

			     void *dev_id)

{

	int r;
@@ -4523,7 +4521,7 @@ static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, 
	return r;

}



static void dispc_free_irq(struct dispc_device *dispc, void *dev_id)

void dispc_free_irq(struct dispc_device *dispc, void *dev_id)

{

	devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc);
@@ -4531,7 +4529,7 @@ static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) 
	dispc->user_data = NULL;

}



static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc)

u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc)

{

	u32 limit = 0;
@@ -4701,47 +4699,6 @@ static void dispc_errata_i734_wa(struct dispc_device *dispc) 
	REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);

}



static const struct dispc_ops dispc_ops = {

	.read_irqstatus = dispc_read_irqstatus,

	.clear_irqstatus = dispc_clear_irqstatus,

	.write_irqenable = dispc_write_irqenable,



	.request_irq = dispc_request_irq,

	.free_irq = dispc_free_irq,



	.runtime_get = dispc_runtime_get,

	.runtime_put = dispc_runtime_put,



	.get_num_ovls = dispc_get_num_ovls,

	.get_num_mgrs = dispc_get_num_mgrs,



	.get_memory_bandwidth_limit = dispc_get_memory_bandwidth_limit,



	.mgr_enable = dispc_mgr_enable,

	.mgr_is_enabled = dispc_mgr_is_enabled,

	.mgr_get_vsync_irq = dispc_mgr_get_vsync_irq,

	.mgr_get_framedone_irq = dispc_mgr_get_framedone_irq,

	.mgr_get_sync_lost_irq = dispc_mgr_get_sync_lost_irq,

	.mgr_go_busy = dispc_mgr_go_busy,

	.mgr_go = dispc_mgr_go,

	.mgr_set_lcd_config = dispc_mgr_set_lcd_config,

	.mgr_check_timings = dispc_mgr_check_timings,

	.mgr_set_timings = dispc_mgr_set_timings,

	.mgr_setup = dispc_mgr_setup,

	.mgr_gamma_size = dispc_mgr_gamma_size,

	.mgr_set_gamma = dispc_mgr_set_gamma,



	.ovl_enable = dispc_ovl_enable,

	.ovl_setup = dispc_ovl_setup,

	.ovl_get_color_modes = dispc_ovl_get_color_modes,



	.wb_get_framedone_irq = dispc_wb_get_framedone_irq,

	.wb_setup = dispc_wb_setup,

	.has_writeback = dispc_has_writeback,

	.wb_go_busy = dispc_wb_go_busy,

	.wb_go = dispc_wb_go,

};



/* DISPC HW IP initialisation */

static const struct of_device_id dispc_of_match[] = {

	{ .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
@@ -4843,7 +4800,6 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) 
	dispc_runtime_put(dispc);



	dss->dispc = dispc;

	dss->dispc_ops = &dispc_ops;



	dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs,

						 dispc);
@@ -4865,7 +4821,6 @@ static void dispc_unbind(struct device *dev, struct device *master, void *data) 
	dss_debugfs_remove_file(dispc->debugfs);



	dss->dispc = NULL;

	dss->dispc_ops = NULL;



	pm_runtime_disable(dev);

drivers/gpu/drm/omapdrm/dss/dss.h

+70 −1
Original line number Diff line number Diff line
@@ -257,7 +257,6 @@ struct dss_device { 
	struct dss_pll	*video2_pll;



	struct dispc_device *dispc;

	const struct dispc_ops *dispc_ops;

	const struct dss_mgr_ops *mgr_ops;

	struct omap_drm_private *mgr_ops_priv;

};
@@ -393,6 +392,76 @@ void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s); 
int dispc_runtime_get(struct dispc_device *dispc);

void dispc_runtime_put(struct dispc_device *dispc);



int dispc_get_num_ovls(struct dispc_device *dispc);

int dispc_get_num_mgrs(struct dispc_device *dispc);



const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,

					    enum omap_plane_id plane);



u32 dispc_read_irqstatus(struct dispc_device *dispc);

void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);

void dispc_write_irqenable(struct dispc_device *dispc, u32 mask);



int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,

			     void *dev_id);

void dispc_free_irq(struct dispc_device *dispc, void *dev_id);



u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,

				   enum omap_channel channel);

u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,

				       enum omap_channel channel);

u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,

				       enum omap_channel channel);

u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc);



u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc);



void dispc_mgr_enable(struct dispc_device *dispc,

			     enum omap_channel channel, bool enable);



bool dispc_mgr_go_busy(struct dispc_device *dispc,

			      enum omap_channel channel);



void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel);



void dispc_mgr_set_lcd_config(struct dispc_device *dispc,

				     enum omap_channel channel,

				     const struct dss_lcd_mgr_config *config);

void dispc_mgr_set_timings(struct dispc_device *dispc,

				  enum omap_channel channel,

				  const struct videomode *vm);

void dispc_mgr_setup(struct dispc_device *dispc,

			    enum omap_channel channel,

			    const struct omap_overlay_manager_info *info);



int dispc_mgr_check_timings(struct dispc_device *dispc,

				   enum omap_channel channel,

				   const struct videomode *vm);



u32 dispc_mgr_gamma_size(struct dispc_device *dispc,

				enum omap_channel channel);

void dispc_mgr_set_gamma(struct dispc_device *dispc,

				enum omap_channel channel,

				const struct drm_color_lut *lut,

				unsigned int length);



int dispc_ovl_setup(struct dispc_device *dispc,

			   enum omap_plane_id plane,

			   const struct omap_overlay_info *oi,

			   const struct videomode *vm, bool mem_to_mem,

			   enum omap_channel channel);



int dispc_ovl_enable(struct dispc_device *dispc,

			    enum omap_plane_id plane, bool enable);



bool dispc_has_writeback(struct dispc_device *dispc);

int dispc_wb_setup(struct dispc_device *dispc,

		   const struct omap_dss_writeback_info *wi,

		   bool mem_to_mem, const struct videomode *vm,

		   enum dss_writeback_channel channel_in);

bool dispc_wb_go_busy(struct dispc_device *dispc);

void dispc_wb_go(struct dispc_device *dispc);



void dispc_enable_sidle(struct dispc_device *dispc);

void dispc_disable_sidle(struct dispc_device *dispc);

drivers/gpu/drm/omapdrm/dss/omapdss.h

+0 −71
Original line number Diff line number Diff line
@@ -379,78 +379,7 @@ int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev, 
void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,

		void (*handler)(void *), void *data);



/* dispc ops */



struct dispc_ops {

	u32 (*read_irqstatus)(struct dispc_device *dispc);

	void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);

	void (*write_irqenable)(struct dispc_device *dispc, u32 mask);



	int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,

			   void *dev_id);

	void (*free_irq)(struct dispc_device *dispc, void *dev_id);



	int (*runtime_get)(struct dispc_device *dispc);

	void (*runtime_put)(struct dispc_device *dispc);



	int (*get_num_ovls)(struct dispc_device *dispc);

	int (*get_num_mgrs)(struct dispc_device *dispc);



	u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc);



	void (*mgr_enable)(struct dispc_device *dispc,

			   enum omap_channel channel, bool enable);

	bool (*mgr_is_enabled)(struct dispc_device *dispc,

			       enum omap_channel channel);

	u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc,

				 enum omap_channel channel);

	u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc,

				     enum omap_channel channel);

	u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc,

				     enum omap_channel channel);

	bool (*mgr_go_busy)(struct dispc_device *dispc,

			    enum omap_channel channel);

	void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel);

	void (*mgr_set_lcd_config)(struct dispc_device *dispc,

				   enum omap_channel channel,

				   const struct dss_lcd_mgr_config *config);

	int (*mgr_check_timings)(struct dispc_device *dispc,

				 enum omap_channel channel,

				 const struct videomode *vm);

	void (*mgr_set_timings)(struct dispc_device *dispc,

				enum omap_channel channel,

				const struct videomode *vm);

	void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel,

			  const struct omap_overlay_manager_info *info);

	u32 (*mgr_gamma_size)(struct dispc_device *dispc,

			      enum omap_channel channel);

	void (*mgr_set_gamma)(struct dispc_device *dispc,

			      enum omap_channel channel,

			      const struct drm_color_lut *lut,

			      unsigned int length);



	int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane,

			  bool enable);

	int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane,

			 const struct omap_overlay_info *oi,

			 const struct videomode *vm, bool mem_to_mem,

			 enum omap_channel channel);



	const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc,

					  enum omap_plane_id plane);



	u32 (*wb_get_framedone_irq)(struct dispc_device *dispc);

	int (*wb_setup)(struct dispc_device *dispc,

		const struct omap_dss_writeback_info *wi,

		bool mem_to_mem, const struct videomode *vm,

		enum dss_writeback_channel channel_in);

	bool (*has_writeback)(struct dispc_device *dispc);

	bool (*wb_go_busy)(struct dispc_device *dispc);

	void (*wb_go)(struct dispc_device *dispc);

};



struct dispc_device *dispc_get_dispc(struct dss_device *dss);

const struct dispc_ops *dispc_get_ops(struct dss_device *dss);



bool omapdss_stack_is_ready(void);

void omapdss_gather_components(struct device *dev);

drivers/gpu/drm/omapdrm/omap_crtc.c

+15 −15
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ int omap_crtc_wait_pending(struct drm_crtc *crtc) 
static void omap_crtc_dss_start_update(struct omap_drm_private *priv,

				       enum omap_channel channel)

{

	priv->dispc_ops->mgr_enable(priv->dispc, channel, true);

	dispc_mgr_enable(priv->dispc, channel, true);

}



/* Called only from the encoder enable/disable and suspend/resume handlers. */
@@ -128,7 +128,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) 
	}



	if (omap_crtc->pipe->output->type == OMAP_DISPLAY_TYPE_HDMI) {

		priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);

		dispc_mgr_enable(priv->dispc, channel, enable);

		omap_crtc->enabled = enable;

		return;

	}
@@ -141,9 +141,9 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) 
		omap_crtc->ignore_digit_sync_lost = true;

	}



	framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,

	framedone_irq = dispc_mgr_get_framedone_irq(priv->dispc,

							       channel);

	vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);

	vsync_irq = dispc_mgr_get_vsync_irq(priv->dispc, channel);



	if (enable) {

		wait = omap_irq_wait_init(dev, vsync_irq, 1);
@@ -163,7 +163,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable) 
			wait = omap_irq_wait_init(dev, vsync_irq, 2);

	}



	priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);

	dispc_mgr_enable(priv->dispc, channel, enable);

	omap_crtc->enabled = enable;



	ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
@@ -186,7 +186,7 @@ static int omap_crtc_dss_enable(struct omap_drm_private *priv, 
	struct drm_crtc *crtc = priv->channels[channel]->crtc;

	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);



	priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,

	dispc_mgr_set_timings(priv->dispc, omap_crtc->channel,

					 &omap_crtc->vm);

	omap_crtc_set_enabled(&omap_crtc->base, true);
@@ -221,7 +221,7 @@ static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv, 
	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);



	DBG("%s", omap_crtc->name);

	priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,

	dispc_mgr_set_lcd_config(priv->dispc, omap_crtc->channel,

					    config);

}
@@ -300,7 +300,7 @@ void omap_crtc_vblank_irq(struct drm_crtc *crtc) 
	 * If the dispc is busy we're racing the flush operation. Try again on

	 * the next vblank interrupt.

	 */

	if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {

	if (dispc_mgr_go_busy(priv->dispc, omap_crtc->channel)) {

		spin_unlock(&crtc->dev->event_lock);

		return;

	}
@@ -426,7 +426,7 @@ static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc) 
		info.cpr_enable = false;

	}



	priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);

	dispc_mgr_setup(priv->dispc, omap_crtc->channel, &info);

}



/* -----------------------------------------------------------------------------
@@ -467,7 +467,7 @@ static void omap_crtc_atomic_enable(struct drm_crtc *crtc, 


	DBG("%s", omap_crtc->name);



	priv->dispc_ops->runtime_get(priv->dispc);

	dispc_runtime_get(priv->dispc);



	/* manual updated display will not trigger vsync irq */

	if (omap_state->manually_updated)
@@ -506,7 +506,7 @@ static void omap_crtc_atomic_disable(struct drm_crtc *crtc, 


	drm_crtc_vblank_off(crtc);



	priv->dispc_ops->runtime_put(priv->dispc);

	dispc_runtime_put(priv->dispc);

}



static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc,
@@ -525,7 +525,7 @@ static enum drm_mode_status omap_crtc_mode_valid(struct drm_crtc *crtc, 
	 * proper DISPC mode later.

	 */

	if (omap_crtc->pipe->output->type != OMAP_DISPLAY_TYPE_DSI) {

		r = priv->dispc_ops->mgr_check_timings(priv->dispc,

		r = dispc_mgr_check_timings(priv->dispc,

						       omap_crtc->channel,

						       &vm);

		if (r)
@@ -643,7 +643,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 
			length = crtc->state->degamma_lut->length /

				sizeof(*lut);

		}

		priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,

		dispc_mgr_set_gamma(priv->dispc, omap_crtc->channel,

					       lut, length);

	}
@@ -668,7 +668,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 
	WARN_ON(ret != 0);



	spin_lock_irq(&crtc->dev->event_lock);

	priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);

	dispc_mgr_go(priv->dispc, omap_crtc->channel);

	omap_crtc_arm_event(crtc);

	spin_unlock_irq(&crtc->dev->event_lock);

}
@@ -858,7 +858,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, 
	 * extracted with dispc_mgr_gamma_size(). If it returns 0

	 * gamma table is not supported.

	 */

	if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {

	if (dispc_mgr_gamma_size(priv->dispc, channel)) {

		unsigned int gamma_lut_size = 256;



		drm_crtc_enable_color_mgmt(crtc, gamma_lut_size, true, 0);