Commit dad947cc authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/gcs: Add manual encodings of GCS instructions 



Define C callable functions for GCS instructions used by the kernel. In
order to avoid ambitious toolchain requirements for GCS support these are
manually encoded, this means we have fixed register numbers which will be
a bit limiting for the compiler but none of these should be used in
sufficiently fast paths for this to be a problem.

Note that GCSSTTR is used to store to EL0.

Reviewed-by: default avatarThiago Jung Bauermann <thiago.bauermann@linaro.org>
Acked-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20241001-arm64-gcs-v13-9-222b78d87eee@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ce0641d4

arch/arm64/include/asm/gcs.h

0 → 100644
+51 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2023 ARM Ltd.

 */

#ifndef __ASM_GCS_H

#define __ASM_GCS_H



#include <asm/types.h>

#include <asm/uaccess.h>



static inline void gcsb_dsync(void)

{

	asm volatile(".inst 0xd503227f" : : : "memory");

}



static inline void gcsstr(u64 *addr, u64 val)

{

	register u64 *_addr __asm__ ("x0") = addr;

	register long _val __asm__ ("x1") = val;



	/* GCSSTTR x1, x0 */

	asm volatile(

		".inst 0xd91f1c01\n"

		:

		: "rZ" (_val), "r" (_addr)

		: "memory");

}



static inline void gcsss1(u64 Xt)

{

	asm volatile (

		"sys #3, C7, C7, #2, %0\n"

		:

		: "rZ" (Xt)

		: "memory");

}



static inline u64 gcsss2(void)

{

	u64 Xt;



	asm volatile(

		"SYSL %0, #3, C7, C7, #3\n"

		: "=r" (Xt)

		:

		: "memory");



	return Xt;

}



#endif

arch/arm64/include/asm/uaccess.h

+22 −0
Original line number Diff line number Diff line
@@ -502,4 +502,26 @@ static inline size_t probe_subpage_writeable(const char __user *uaddr, 


#endif /* CONFIG_ARCH_HAS_SUBPAGE_FAULTS */



#ifdef CONFIG_ARM64_GCS



static inline int gcssttr(unsigned long __user *addr, unsigned long val)

{

	register unsigned long __user *_addr __asm__ ("x0") = addr;

	register unsigned long _val __asm__ ("x1") = val;

	int err = 0;



	/* GCSSTTR x1, x0 */

	asm volatile(

		"1: .inst 0xd91f1c01\n"

		"2: \n"

		_ASM_EXTABLE_UACCESS_ERR(1b, 2b, %w0)

		: "+r" (err)

		: "rZ" (_val), "r" (_addr)

		: "memory");



	return err;

}



#endif /* CONFIG_ARM64_GCS */



#endif /* __ASM_UACCESS_H */