Commit dadc3a6b authored by Russell King (Oracle)'s avatar Russell King (Oracle) Committed by Jakub Kicinski
Browse files

net: stmmac: dwc-qos: remove tegra_eqos_init() 



tegra_eqos_init() initialises the 1US TIC counter for the EEE timers.
However, the DWGMAC core is reset after this write, which clears
this register to its default.

However, dwmac4_core_init() configures this register using the same
clock, which happens after reset - thus this is the write which
ensures that the register is correctly configured.

Therefore, tegra_eqos_init() is not required and is removed. This also
means eqos->clk_slave can also be removed.

Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1u3Vuf-000E7g-U4@rmk-PC.armlinux.org.uk


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 505b9309

drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c

+1 −23
Original line number Diff line number Diff line
@@ -29,7 +29,6 @@ struct tegra_eqos { 
	void __iomem *regs;



	struct reset_control *rst;

	struct clk *clk_slave;



	struct gpio_desc *reset;

};
@@ -199,20 +198,6 @@ static void tegra_eqos_fix_speed(void *priv, int speed, unsigned int mode) 
	}

}



static int tegra_eqos_init(struct platform_device *pdev, void *priv)

{

	struct tegra_eqos *eqos = priv;

	unsigned long rate;

	u32 value;



	rate = clk_get_rate(eqos->clk_slave);



	value = (rate / 1000000) - 1;

	writel(value, eqos->regs + GMAC_1US_TIC_COUNTER);



	return 0;

}



static int tegra_eqos_probe(struct platform_device *pdev,

			    struct plat_stmmacenet_data *plat_dat,

			    struct stmmac_resources *res)
@@ -227,7 +212,6 @@ static int tegra_eqos_probe(struct platform_device *pdev, 


	eqos->dev = &pdev->dev;

	eqos->regs = res->addr;

	eqos->clk_slave = plat_dat->stmmac_clk;



	if (!is_of_node(dev->fwnode))

		goto bypass_clk_reset_gpio;
@@ -267,17 +251,11 @@ static int tegra_eqos_probe(struct platform_device *pdev, 
bypass_clk_reset_gpio:

	plat_dat->fix_mac_speed = tegra_eqos_fix_speed;

	plat_dat->set_clk_tx_rate = stmmac_set_clk_tx_rate;

	plat_dat->init = tegra_eqos_init;

	plat_dat->bsp_priv = eqos;

	plat_dat->flags |= STMMAC_FLAG_SPH_DISABLE;



	err = tegra_eqos_init(pdev, eqos);

	if (err < 0)

		goto reset;



	return 0;

reset:

	reset_control_assert(eqos->rst);



reset_phy:

	gpiod_set_value(eqos->reset, 1);