Commit db217d08 authored by Gangliang Xie's avatar Gangliang Xie Committed by Alex Deucher
Browse files

drm/amd/ras: Add table reset func for pmfw eeprom 



add table reset func for pmfw eeprom, add smu eeprom control
structure

Signed-off-by: default avatarGangliang Xie <ganglxie@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0e5eaa8d

drivers/gpu/drm/amd/ras/rascore/ras.h

+1 −0
Original line number Diff line number Diff line
@@ -313,6 +313,7 @@ struct ras_core_context { 


	bool ras_eeprom_supported;

	struct ras_eeprom_control ras_eeprom;

	struct ras_fw_eeprom_control ras_fw_eeprom;



	struct ras_psp ras_psp;

	struct ras_umc ras_umc;

drivers/gpu/drm/amd/ras/rascore/ras_cmd.c

+7 −2
Original line number Diff line number Diff line
@@ -146,8 +146,13 @@ static int ras_cmd_clear_bad_page_info(struct ras_core_context *ras_core, 
	if (cmd->input_size != sizeof(struct ras_cmd_dev_handle))

		return RAS_CMD__ERROR_INVALID_INPUT_SIZE;



	if (ras_fw_eeprom_supported(ras_core)) {

		if (ras_fw_eeprom_reset_table(ras_core))

			return RAS_CMD__ERROR_GENERIC;

	} else {

		if (ras_eeprom_reset_table(ras_core))

			return RAS_CMD__ERROR_GENERIC;

	}



	if (ras_umc_clean_badpage_data(ras_core))

		return RAS_CMD__ERROR_GENERIC;

drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.c

+29 −0
Original line number Diff line number Diff line
@@ -161,3 +161,32 @@ int ras_fw_erase_ras_table(struct ras_core_context *ras_core, 
	return sys_func->mp1_send_eeprom_msg(ras_core,

			RAS_SMU_EraseRasTable, 0, result);

}



int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core)

{

	struct ras_fw_eeprom_control *control = &ras_core->ras_fw_eeprom;

	u32 erase_res = 0;

	int res;



	mutex_lock(&control->ras_tbl_mutex);



	res = ras_fw_erase_ras_table(ras_core, &erase_res);

	if (res || erase_res) {

		RAS_DEV_WARN(ras_core->dev, "RAS EEPROM reset failed, res:%d result:%d",

									res, erase_res);

		if (!res)

			res = -EIO;

	}



	control->ras_num_recs = 0;

	control->bad_channel_bitmap = 0;

	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_PAGE_NUM,

		&control->ras_num_recs);

	ras_core_event_notify(ras_core, RAS_EVENT_ID__UPDATE_BAD_CHANNEL_BITMAP,

		&control->bad_channel_bitmap);

	control->update_channel_flag = false;



	mutex_unlock(&control->ras_tbl_mutex);



	return res;

}

drivers/gpu/drm/amd/ras/rascore/ras_eeprom_fw.h

+26 −0
Original line number Diff line number Diff line
@@ -24,6 +24,31 @@ 
#ifndef __RAS_EEPROM_FW_H__

#define __RAS_EEPROM_FW_H__



struct ras_fw_eeprom_control {

	uint32_t version;

	/* record threshold */

	int record_threshold_config;

	uint32_t record_threshold_count;

	bool update_channel_flag;



	/* Number of records in the table.

	 */

	u32 ras_num_recs;



	/* Maximum possible number of records

	 * we could store, i.e. the maximum capacity

	 * of the table.

	 */

	u32 ras_max_record_count;



	/* Protect table access via this mutex.

	 */

	struct mutex ras_tbl_mutex;



	/* Record channel info which occurred bad pages

	 */

	u32 bad_channel_bitmap;

};



void ras_fw_init_feature_flags(struct ras_core_context *ras_core);

bool ras_fw_eeprom_supported(struct ras_core_context *ras_core);
@@ -41,5 +66,6 @@ int ras_fw_get_badpage_ipid(struct ras_core_context *ras_core, 
				    uint16_t index, uint64_t *ipid);

int ras_fw_erase_ras_table(struct ras_core_context *ras_core,

				   uint32_t *result);

int ras_fw_eeprom_reset_table(struct ras_core_context *ras_core);



#endif