Commit db99675e authored by Tony Luck's avatar Tony Luck Committed by Borislav Petkov (AMD)
Browse files

x86/resctrl: Switch to new Intel CPU model defines 



New CPU #defines encode vendor and family as well as model.

  [ bp: Squash two resctrl patches into one. ]

Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/all/20240424181514.41848-1-tony.luck%40intel.com
parent 375a7564

arch/x86/kernel/cpu/resctrl/core.c

+5 −5
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ 
#include <linux/cacheinfo.h>

#include <linux/cpuhotplug.h>



#include <asm/intel-family.h>

#include <asm/cpu_device_id.h>

#include <asm/resctrl.h>

#include "internal.h"
@@ -821,18 +821,18 @@ static __init bool get_rdt_mon_resources(void) 


static __init void __check_quirks_intel(void)

{

	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_HASWELL_X:

	switch (boot_cpu_data.x86_vfm) {

	case INTEL_HASWELL_X:

		if (!rdt_options[RDT_FLAG_L3_CAT].force_off)

			cache_alloc_hsw_probe();

		break;

	case INTEL_FAM6_SKYLAKE_X:

	case INTEL_SKYLAKE_X:

		if (boot_cpu_data.x86_stepping <= 4)

			set_rdt_options("!cmt,!mbmtotal,!mbmlocal,!l3cat");

		else

			set_rdt_options("!l3cat");

		fallthrough;

	case INTEL_FAM6_BROADWELL_X:

	case INTEL_BROADWELL_X:

		intel_rdt_mbm_apply_quirk();

		break;

	}

arch/x86/kernel/cpu/resctrl/pseudo_lock.c

+11 −11
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#include <linux/uaccess.h>



#include <asm/cacheflush.h>

#include <asm/intel-family.h>

#include <asm/cpu_device_id.h>

#include <asm/resctrl.h>

#include <asm/perf_event.h>
@@ -88,8 +88,8 @@ static u64 get_prefetch_disable_bits(void) 
	    boot_cpu_data.x86 != 6)

		return 0;



	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_BROADWELL_X:

	switch (boot_cpu_data.x86_vfm) {

	case INTEL_BROADWELL_X:

		/*

		 * SDM defines bits of MSR_MISC_FEATURE_CONTROL register

		 * as:
@@ -100,8 +100,8 @@ static u64 get_prefetch_disable_bits(void) 
		 * 63:4 Reserved

		 */

		return 0xF;

	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:

	case INTEL_ATOM_GOLDMONT:

	case INTEL_ATOM_GOLDMONT_PLUS:

		/*

		 * SDM defines bits of MSR_MISC_FEATURE_CONTROL register

		 * as:
@@ -1084,9 +1084,9 @@ static int measure_l2_residency(void *_plr) 
	 *     L2_HIT   02H

	 *     L2_MISS  10H

	 */

	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_ATOM_GOLDMONT:

	case INTEL_FAM6_ATOM_GOLDMONT_PLUS:

	switch (boot_cpu_data.x86_vfm) {

	case INTEL_ATOM_GOLDMONT:

	case INTEL_ATOM_GOLDMONT_PLUS:

		perf_miss_attr.config = X86_CONFIG(.event = 0xd1,

						   .umask = 0x10);

		perf_hit_attr.config = X86_CONFIG(.event = 0xd1,
@@ -1123,8 +1123,8 @@ static int measure_l3_residency(void *_plr) 
	 *       MISS      41H

	 */



	switch (boot_cpu_data.x86_model) {

	case INTEL_FAM6_BROADWELL_X:

	switch (boot_cpu_data.x86_vfm) {

	case INTEL_BROADWELL_X:

		/* On BDW the hit event counts references, not hits */

		perf_hit_attr.config = X86_CONFIG(.event = 0x2e,

						  .umask = 0x4f);
@@ -1142,7 +1142,7 @@ static int measure_l3_residency(void *_plr) 
	 */



	counts.miss_after -= counts.miss_before;

	if (boot_cpu_data.x86_model == INTEL_FAM6_BROADWELL_X) {

	if (boot_cpu_data.x86_vfm == INTEL_BROADWELL_X) {

		/*

		 * On BDW references and misses are counted, need to adjust.

		 * Sometimes the "hits" counter is a bit more than the