Commit dbb2c3ad authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.17-2025-08-20' of... 

Merge tag 'amd-drm-fixes-6.17-2025-08-20' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.17-2025-08-20:

amdgpu:
- Replay fixes
- SMU14 fix
- Null check DC fixes
- DCE6 DC fixes
- Misc DC fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://lore.kernel.org/r/20250820194636.101975-1-alexander.deucher@amd.com
parents 98c4a3f4 297a4833

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −0
Original line number Diff line number Diff line
@@ -7792,6 +7792,9 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, 
	struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);

	int ret;



	if (WARN_ON(unlikely(!old_con_state || !new_con_state)))

		return -EINVAL;



	trace_amdgpu_dm_connector_atomic_check(new_con_state);



	if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

+19 −0
Original line number Diff line number Diff line
@@ -299,6 +299,25 @@ static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable) 
	irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);



	if (enable) {

		struct dc *dc = adev->dm.dc;

		struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);

		struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;

		struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;

		bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||

								pr->config.replay_supported;



		/*

		 * IPS & self-refresh feature can cause vblank counter resets between

		 * vblank disable and enable.

		 * It may cause system stuck due to waiting for the vblank counter.

		 * Call this function to estimate missed vblanks by using timestamps and

		 * update the vblank counter in DRM.

		 */

		if (dc->caps.ips_support &&

			dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&

			sr_supported && vblank->config.disable_immediate)

			drm_crtc_vblank_restore(crtc);



		/* vblank irq on -> Only need vupdate irq in vrr mode */

		if (amdgpu_dm_crtc_vrr_active(acrtc_state))

			rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);

drivers/gpu/drm/amd/display/dc/bios/bios_parser.c

+1 −4
Original line number Diff line number Diff line
@@ -174,11 +174,8 @@ static struct graphics_object_id bios_parser_get_connector_id( 
		return object_id;

	}



	if (tbl->ucNumberOfObjects <= i) {

		dm_error("Can't find connector id %d in connector table of size %d.\n",

			 i, tbl->ucNumberOfObjects);

	if (tbl->ucNumberOfObjects <= i)

		return object_id;

	}



	id = le16_to_cpu(tbl->asObjects[i].usObjectID);

	object_id = object_id_from_bios_object_id(id);

drivers/gpu/drm/amd/display/dc/bios/command_table.c

+1 −1
Original line number Diff line number Diff line
@@ -993,7 +993,7 @@ static enum bp_result set_pixel_clock_v3( 
	allocation.sPCLKInput.usFbDiv =

			cpu_to_le16((uint16_t)bp_params->feedback_divider);

	allocation.sPCLKInput.ucFracFbDiv =

			(uint8_t)bp_params->fractional_feedback_divider;

			(uint8_t)(bp_params->fractional_feedback_divider / 100000);

	allocation.sPCLKInput.ucPostDiv =

			(uint8_t)bp_params->pixel_clock_post_divider;

drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c

+5 −9
Original line number Diff line number Diff line
@@ -72,9 +72,9 @@ static const struct state_dependent_clocks dce80_max_clks_by_state[] = { 
/* ClocksStateLow */

{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},

/* ClocksStateNominal */

{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },

{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },

/* ClocksStatePerformance */

{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };

{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };



int dentist_get_divider_from_did(int did)

{
@@ -391,8 +391,6 @@ static void dce_pplib_apply_display_requirements( 
{

	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;



	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);



	dce110_fill_display_configs(context, pp_display_cfg);



	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)
@@ -405,11 +403,9 @@ static void dce_update_clocks(struct clk_mgr *clk_mgr_base, 
{

	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dm_pp_power_level_change_request level_change_req;

	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;



	/*TODO: W/A for dal3 linux, investigate why this works */

	if (!clk_mgr_dce->dfs_bypass_active)

		patched_disp_clk = patched_disp_clk * 115 / 100;

	const int max_disp_clk =

		clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;

	int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);



	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

	/* get max clock state from PPLIB */