Commit dbd57932 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Mauro Carvalho Chehab
Browse files

media: iris: Add support for SM8750 (VPU v3.5) 



Add support for SM8750 Iris codec with major differences against
previous generation SM8650:

1. New clocks and new resets, thus new power up and power down
   sequences,

2. New WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 register programmed
   during boot-up

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarDikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Reviewed-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: default avatarBryan O'Donoghue <bod@kernel.org>
Signed-off-by: default avatarHans Verkuil <hverkuil+cisco@kernel.org>
parent 1f01a498

drivers/media/platform/qcom/iris/iris_platform_common.h

+5 −1
Original line number Diff line number Diff line
@@ -38,11 +38,15 @@ extern struct iris_platform_data qcs8300_data; 
extern struct iris_platform_data sm8250_data;

extern struct iris_platform_data sm8550_data;

extern struct iris_platform_data sm8650_data;

extern struct iris_platform_data sm8750_data;



enum platform_clk_type {

	IRIS_AXI_CLK,

	IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */

	IRIS_CTRL_CLK,

	IRIS_HW_CLK,

	IRIS_AXI1_CLK,

	IRIS_CTRL_FREERUN_CLK,

	IRIS_HW_FREERUN_CLK,

};



struct platform_clk_data {

drivers/media/platform/qcom/iris/iris_platform_gen2.c

+68 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2025 Linaro Ltd

 */



#include "iris_core.h"
@@ -12,6 +13,7 @@ 


#include "iris_platform_qcs8300.h"

#include "iris_platform_sm8650.h"

#include "iris_platform_sm8750.h"



#define VIDEO_ARCH_LX 1
@@ -463,6 +465,72 @@ struct iris_platform_data sm8650_data = { 
	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),

};



struct iris_platform_data sm8750_data = {

	.get_instance = iris_hfi_gen2_get_instance,

	.init_hfi_command_ops = iris_hfi_gen2_command_ops_init,

	.init_hfi_response_ops = iris_hfi_gen2_response_ops_init,

	.vpu_ops = &iris_vpu35_ops,

	.set_preset_registers = iris_set_sm8550_preset_registers,

	.icc_tbl = sm8550_icc_table,

	.icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),

	.clk_rst_tbl = sm8750_clk_reset_table,

	.clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table),

	.bw_tbl_dec = sm8550_bw_table_dec,

	.bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),

	.pmdomain_tbl = sm8550_pmdomain_table,

	.pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table),

	.opp_pd_tbl = sm8550_opp_pd_table,

	.opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),

	.clk_tbl = sm8750_clk_table,

	.clk_tbl_size = ARRAY_SIZE(sm8750_clk_table),

	/* Upper bound of DMA address range */

	.dma_mask = 0xe0000000 - 1,

	.fwname = "qcom/vpu/vpu35_p4.mbn",

	.pas_id = IRIS_PAS_ID,

	.inst_caps = &platform_inst_cap_sm8550,

	.inst_fw_caps = inst_fw_cap_sm8550,

	.inst_fw_caps_size = ARRAY_SIZE(inst_fw_cap_sm8550),

	.tz_cp_config_data = &tz_cp_config_sm8550,

	.core_arch = VIDEO_ARCH_LX,

	.hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,

	.ubwc_config = &ubwc_config_sm8550,

	.num_vpp_pipe = 4,

	.max_session_count = 16,

	.max_core_mbpf = NUM_MBS_8K * 2,

	.input_config_params_default =

		sm8550_vdec_input_config_params_default,

	.input_config_params_default_size =

		ARRAY_SIZE(sm8550_vdec_input_config_params_default),

	.input_config_params_hevc =

		sm8550_vdec_input_config_param_hevc,

	.input_config_params_hevc_size =

		ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),

	.input_config_params_vp9 =

		sm8550_vdec_input_config_param_vp9,

	.input_config_params_vp9_size =

		ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),

	.output_config_params =

		sm8550_vdec_output_config_params,

	.output_config_params_size =

		ARRAY_SIZE(sm8550_vdec_output_config_params),

	.dec_input_prop = sm8550_vdec_subscribe_input_properties,

	.dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),

	.dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,

	.dec_output_prop_avc_size =

		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),

	.dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,

	.dec_output_prop_hevc_size =

		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),

	.dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,

	.dec_output_prop_vp9_size =

		ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),



	.dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,

	.dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),

	.dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,

	.dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),

};



/*

 * Shares most of SM8550 data except:

 * - inst_caps to platform_inst_cap_qcs8300

drivers/media/platform/qcom/iris/iris_platform_sm8750.h

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2025 Linaro Ltd

 */



#ifndef __MEDIA_IRIS_PLATFORM_SM8750_H__

#define __MEDIA_IRIS_PLATFORM_SM8750_H__



static const char * const sm8750_clk_reset_table[] = {

	"bus0", "bus1", "core", "vcodec0_core"

};



static const struct platform_clk_data sm8750_clk_table[] = {

	{IRIS_AXI_CLK,		"iface"			},

	{IRIS_CTRL_CLK,		"core"			},

	{IRIS_HW_CLK,		"vcodec0_core"		},

	{IRIS_AXI1_CLK,		"iface1"		},

	{IRIS_CTRL_FREERUN_CLK,	"core_freerun"		},

	{IRIS_HW_FREERUN_CLK,	"vcodec0_core_freerun"	},

};



#endif

drivers/media/platform/qcom/iris/iris_probe.c

+4 −0
Original line number Diff line number Diff line
@@ -353,6 +353,10 @@ static const struct of_device_id iris_dt_match[] = { 
		.compatible = "qcom,sm8650-iris",

		.data = &sm8650_data,

	},

	{

		.compatible = "qcom,sm8750-iris",

		.data = &sm8750_data,

	},

	{ },

};

MODULE_DEVICE_TABLE(of, iris_dt_match);

drivers/media/platform/qcom/iris/iris_vpu3x.c

+166 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.

 * Copyright (c) 2025 Linaro Ltd

 */



#include <linux/iopoll.h>
@@ -24,6 +25,8 @@ 
#define NOC_LPI_STATUS_ACTIVE		BIT(2) /* Indicates the NOC is active */

#define WRAPPER_CORE_CLOCK_CONFIG		(WRAPPER_BASE_OFFS + 0x88)

#define CORE_CLK_RUN				0x0

/* VPU v3.5 */

#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0	(WRAPPER_BASE_OFFS + 0x78)



#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG		(WRAPPER_TZ_BASE_OFFS + 0x14)

#define CTL_AXI_CLK_HALT			BIT(0)
@@ -55,6 +58,8 @@ 
#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL	(AON_BASE_OFFS + 0x20)

#define NOC_HALT				BIT(0)

#define AON_WRAPPER_SPARE			(AON_BASE_OFFS + 0x28)

#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL	(AON_BASE_OFFS + 0x2C)

#define AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS	(AON_BASE_OFFS + 0x30)



static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)

{
@@ -253,6 +258,158 @@ static int iris_vpu33_power_off_controller(struct iris_core *core) 
	return 0;

}



static int iris_vpu35_power_on_hw(struct iris_core *core)

{

	int ret;



	ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);

	if (ret)

		return ret;



	ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK);

	if (ret)

		goto err_disable_power;



	ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK);

	if (ret)

		goto err_disable_axi_clk;



	ret = iris_prepare_enable_clock(core, IRIS_HW_CLK);

	if (ret)

		goto err_disable_hw_free_clk;



	ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true);

	if (ret)

		goto err_disable_hw_clk;



	return 0;



err_disable_hw_clk:

	iris_disable_unprepare_clock(core, IRIS_HW_CLK);

err_disable_hw_free_clk:

	iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);

err_disable_axi_clk:

	iris_disable_unprepare_clock(core, IRIS_AXI_CLK);

err_disable_power:

	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]);



	return ret;

}



static void iris_vpu35_power_off_hw(struct iris_core *core)

{

	iris_vpu33_power_off_hardware(core);



	iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);

	iris_disable_unprepare_clock(core, IRIS_AXI_CLK);

}



static int iris_vpu35_power_off_controller(struct iris_core *core)

{

	u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;

	unsigned int count = 0;

	u32 val = 0;

	bool handshake_done, handshake_busy;

	int ret;



	writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);



	writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);



	ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,

				 val, val & BIT(0), 200, 2000);

	if (ret)

		goto disable_power;



	writel(0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);



	/* Retry up to 1000 times as recommended by hardware documentation */

	do {

		/* set MNoC to low power */

		writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);



		udelay(15);



		val = readl(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS);



		handshake_done = val & NOC_LPI_STATUS_DONE;

		handshake_busy = val & (NOC_LPI_STATUS_DENY | NOC_LPI_STATUS_ACTIVE);



		if (handshake_done || !handshake_busy)

			break;



		writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);



		udelay(15);



	} while (++count < 1000);



	if (!handshake_done && handshake_busy)

		dev_err(core->dev, "LPI handshake timeout\n");



	ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,

				 val, val & BIT(0), 200, 2000);

	if (ret)

		goto disable_power;



	writel(0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);



	writel(0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);



	ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,

				 val, val == 0, 200, 2000);

	if (ret)

		goto disable_power;



disable_power:

	iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);

	iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);

	iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);



	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);



	reset_control_bulk_reset(clk_rst_tbl_size, core->resets);



	return 0;

}



static int iris_vpu35_power_on_controller(struct iris_core *core)

{

	int ret;



	ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);

	if (ret)

		return ret;



	ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);

	if (ret)

		goto err_disable_power;



	ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);

	if (ret)

		goto err_disable_axi1_clk;



	ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);

	if (ret)

		goto err_disable_ctrl_free_clk;



	return 0;



err_disable_ctrl_free_clk:

	iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);

err_disable_axi1_clk:

	iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);

err_disable_power:

	iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);



	return ret;

}



static void iris_vpu35_program_bootup_registers(struct iris_core *core)

{

	writel(0x1, core->reg_base + WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0);

}



static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t data_size)

{

	struct platform_inst_caps *caps = inst->core->iris_platform_data->inst_caps;
@@ -305,3 +462,12 @@ const struct vpu_ops iris_vpu33_ops = { 
	.power_on_controller = iris_vpu_power_on_controller,

	.calc_freq = iris_vpu3x_calculate_frequency,

};



const struct vpu_ops iris_vpu35_ops = {

	.power_off_hw = iris_vpu35_power_off_hw,

	.power_on_hw = iris_vpu35_power_on_hw,

	.power_off_controller = iris_vpu35_power_off_controller,

	.power_on_controller = iris_vpu35_power_on_controller,

	.program_bootup_registers = iris_vpu35_program_bootup_registers,

	.calc_freq = iris_vpu3x_calculate_frequency,

};