Commit dbe0ed33 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'renesas-pinctrl-for-v6.10-tag1' of... 

Merge tag 'renesas-pinctrl-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers

 into devel

pinctrl: renesas: Updates for v6.10

  - Add external interrupt pin groups on R-Car V4M,
  - Miscellaneous fixes and improvements.

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents 782b72a2 cd27553b

Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

+2 −0
Original line number Diff line number Diff line
@@ -120,7 +120,9 @@ additionalProperties: 
        slew-rate: true

        gpio-hog: true

        gpios: true

        input: true

        input-enable: true

        output-enable: true

        output-high: true

        output-low: true

        line-name: true

drivers/pinctrl/renesas/pfc-r8a779h0.c

+124 −12
Original line number Diff line number Diff line
@@ -75,10 +75,10 @@ 
#define GPSR0_9		F_(MSIOF5_SYNC,		IP1SR0_7_4)

#define GPSR0_8		F_(MSIOF5_SS1,		IP1SR0_3_0)

#define GPSR0_7		F_(MSIOF5_SS2,		IP0SR0_31_28)

#define GPSR0_6		F_(IRQ0,		IP0SR0_27_24)

#define GPSR0_5		F_(IRQ1,		IP0SR0_23_20)

#define GPSR0_4		F_(IRQ2,		IP0SR0_19_16)

#define GPSR0_3		F_(IRQ3,		IP0SR0_15_12)

#define GPSR0_6		F_(IRQ0_A,		IP0SR0_27_24)

#define GPSR0_5		F_(IRQ1_A,		IP0SR0_23_20)

#define GPSR0_4		F_(IRQ2_A,		IP0SR0_19_16)

#define GPSR0_3		F_(IRQ3_A,		IP0SR0_15_12)

#define GPSR0_2		F_(GP0_02,		IP0SR0_11_8)

#define GPSR0_1		F_(GP0_01,		IP0SR0_7_4)

#define GPSR0_0		F_(GP0_00,		IP0SR0_3_0)
@@ -265,10 +265,10 @@ 
#define IP0SR0_3_0	F_(0, 0)		FM(ERROROUTC_N_B)	FM(TCLK2_B)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_7_4	F_(0, 0)		FM(MSIOF3_SS1)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_11_8	F_(0, 0)		FM(MSIOF3_SS2)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_15_12	FM(IRQ3)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_19_16	FM(IRQ2)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_23_20	FM(IRQ1)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_27_24	FM(IRQ0)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_15_12	FM(IRQ3_A)		FM(MSIOF3_SCK)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_19_16	FM(IRQ2_A)		FM(MSIOF3_TXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_23_20	FM(IRQ1_A)		FM(MSIOF3_RXD)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_27_24	FM(IRQ0_A)		FM(MSIOF3_SYNC)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)

#define IP0SR0_31_28	FM(MSIOF5_SS2)		F_(0, 0)		F_(0, 0)	F_(0, 0)	F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)



/* IP1SR0 */		/* 0 */			/* 1 */			/* 2 */		/* 3		4	 5	  6	   7	    8	     9	      A	       B	C	 D	  E	   F */
@@ -672,16 +672,16 @@ static const u16 pinmux_data[] = { 


	PINMUX_IPSR_GPSR(IP0SR0_11_8,	MSIOF3_SS2),



	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3),

	PINMUX_IPSR_GPSR(IP0SR0_15_12,	IRQ3_A),

	PINMUX_IPSR_GPSR(IP0SR0_15_12,	MSIOF3_SCK),



	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2),

	PINMUX_IPSR_GPSR(IP0SR0_19_16,	IRQ2_A),

	PINMUX_IPSR_GPSR(IP0SR0_19_16,	MSIOF3_TXD),



	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1),

	PINMUX_IPSR_GPSR(IP0SR0_23_20,	IRQ1_A),

	PINMUX_IPSR_GPSR(IP0SR0_23_20,	MSIOF3_RXD),



	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0),

	PINMUX_IPSR_GPSR(IP0SR0_27_24,	IRQ0_A),

	PINMUX_IPSR_GPSR(IP0SR0_27_24,	MSIOF3_SYNC),



	PINMUX_IPSR_GPSR(IP0SR0_31_28,	MSIOF5_SS2),
@@ -1660,6 +1660,90 @@ static const unsigned int i2c3_mux[] = { 
	SDA3_MARK, SCL3_MARK,

};



/* - INTC-EX ---------------------------------------------------------------- */

static const unsigned int intc_ex_irq0_a_pins[] = {

	/* IRQ0_A */

	RCAR_GP_PIN(0, 6),

};

static const unsigned int intc_ex_irq0_a_mux[] = {

	IRQ0_A_MARK,

};

static const unsigned int intc_ex_irq0_b_pins[] = {

	/* IRQ0_B */

	RCAR_GP_PIN(1, 20),

};

static const unsigned int intc_ex_irq0_b_mux[] = {

	IRQ0_B_MARK,

};



static const unsigned int intc_ex_irq1_a_pins[] = {

	/* IRQ1_A */

	RCAR_GP_PIN(0, 5),

};

static const unsigned int intc_ex_irq1_a_mux[] = {

	IRQ1_A_MARK,

};

static const unsigned int intc_ex_irq1_b_pins[] = {

	/* IRQ1_B */

	RCAR_GP_PIN(1, 21),

};

static const unsigned int intc_ex_irq1_b_mux[] = {

	IRQ1_B_MARK,

};



static const unsigned int intc_ex_irq2_a_pins[] = {

	/* IRQ2_A */

	RCAR_GP_PIN(0, 4),

};

static const unsigned int intc_ex_irq2_a_mux[] = {

	IRQ2_A_MARK,

};

static const unsigned int intc_ex_irq2_b_pins[] = {

	/* IRQ2_B */

	RCAR_GP_PIN(0, 13),

};

static const unsigned int intc_ex_irq2_b_mux[] = {

	IRQ2_B_MARK,

};



static const unsigned int intc_ex_irq3_a_pins[] = {

	/* IRQ3_A */

	RCAR_GP_PIN(0, 3),

};

static const unsigned int intc_ex_irq3_a_mux[] = {

	IRQ3_A_MARK,

};

static const unsigned int intc_ex_irq3_b_pins[] = {

	/* IRQ3_B */

	RCAR_GP_PIN(1, 23),

};

static const unsigned int intc_ex_irq3_b_mux[] = {

	IRQ3_B_MARK,

};



static const unsigned int intc_ex_irq4_a_pins[] = {

	/* IRQ4_A */

	RCAR_GP_PIN(1, 17),

};

static const unsigned int intc_ex_irq4_a_mux[] = {

	IRQ4_A_MARK,

};

static const unsigned int intc_ex_irq4_b_pins[] = {

	/* IRQ4_B */

	RCAR_GP_PIN(2, 3),

};

static const unsigned int intc_ex_irq4_b_mux[] = {

	IRQ4_B_MARK,

};



static const unsigned int intc_ex_irq5_pins[] = {

	/* IRQ5 */

	RCAR_GP_PIN(2, 2),

};

static const unsigned int intc_ex_irq5_mux[] = {

	IRQ5_MARK,

};



/* - MMC -------------------------------------------------------------------- */

static const unsigned int mmc_data_pins[] = {

	/* MMC_SD_D[0:3], MMC_D[4:7] */
@@ -2416,6 +2500,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { 
	SH_PFC_PIN_GROUP(i2c2),

	SH_PFC_PIN_GROUP(i2c3),



	SH_PFC_PIN_GROUP(intc_ex_irq0_a),

	SH_PFC_PIN_GROUP(intc_ex_irq0_b),

	SH_PFC_PIN_GROUP(intc_ex_irq1_a),

	SH_PFC_PIN_GROUP(intc_ex_irq1_b),

	SH_PFC_PIN_GROUP(intc_ex_irq2_a),

	SH_PFC_PIN_GROUP(intc_ex_irq2_b),

	SH_PFC_PIN_GROUP(intc_ex_irq3_a),

	SH_PFC_PIN_GROUP(intc_ex_irq3_b),

	SH_PFC_PIN_GROUP(intc_ex_irq4_a),

	SH_PFC_PIN_GROUP(intc_ex_irq4_b),

	SH_PFC_PIN_GROUP(intc_ex_irq5),



	BUS_DATA_PIN_GROUP(mmc_data, 1),

	BUS_DATA_PIN_GROUP(mmc_data, 4),

	BUS_DATA_PIN_GROUP(mmc_data, 8),
@@ -2629,6 +2725,20 @@ static const char * const i2c3_groups[] = { 
	"i2c3",

};



static const char * const intc_ex_groups[] = {

	"intc_ex_irq0_a",

	"intc_ex_irq0_b",

	"intc_ex_irq1_a",

	"intc_ex_irq1_b",

	"intc_ex_irq2_a",

	"intc_ex_irq2_b",

	"intc_ex_irq3_a",

	"intc_ex_irq3_b",

	"intc_ex_irq4_a",

	"intc_ex_irq4_b",

	"intc_ex_irq5",

};



static const char * const mmc_groups[] = {

	"mmc_data1",

	"mmc_data4",
@@ -2813,6 +2923,8 @@ static const struct sh_pfc_function pinmux_functions[] = { 
	SH_PFC_FUNCTION(i2c2),

	SH_PFC_FUNCTION(i2c3),



	SH_PFC_FUNCTION(intc_ex),



	SH_PFC_FUNCTION(mmc),



	SH_PFC_FUNCTION(msiof0),

drivers/pinctrl/renesas/pinctrl-rzg2l.c

+16 −2
Original line number Diff line number Diff line
@@ -892,6 +892,8 @@ static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps 
		val = PVDD_1800;

		break;

	case 2500:

		if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))

			return -EINVAL;

		val = PVDD_2500;

		break;

	case 3300:
@@ -2045,7 +2047,9 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 


	for (unsigned int i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) {

		struct irq_data *data;

		unsigned long flags;

		unsigned int virq;

		int ret;



		if (!pctrl->hwirq[i])

			continue;
@@ -2063,8 +2067,18 @@ static void rzg2l_gpio_irq_restore(struct rzg2l_pinctrl *pctrl) 
			continue;

		}



		if (!irqd_irq_disabled(data))

		/*

		 * This has to be atomically executed to protect against a concurrent

		 * interrupt.

		 */

		raw_spin_lock_irqsave(&pctrl->lock.rlock, flags);

		ret = rzg2l_gpio_irq_set_type(data, irqd_get_trigger_type(data));

		if (!ret && !irqd_irq_disabled(data))

			rzg2l_gpio_irq_enable(data);

		raw_spin_unlock_irqrestore(&pctrl->lock.rlock, flags);



		if (ret)

			dev_crit(pctrl->dev, "Failed to set IRQ type for virq=%u\n", virq);

	}

}